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AM79C961KCW

PCnet™-ISA+ Jumperless Single-Chip Ethernet Controller for ISA

Advanced Micro Devices 

PRELIMINARY

AMD

and proceeds into a power savings mode. All outputs

will be placed in their normal reset condition. All

PCnet-ISA+ controller inputs will be ignored except for

the SLEEP pin itself. Deassertion of SLEEP results in

wake-up. The system must delay the starting of the

network controller by 0.5 seconds to allow internal ana-

log circuits to stabilize.

SMA

Shared Memory Architecture Input

This pin is sampled after the hardware RESET se-

quence. The pin must be pulled permanently LOW for

operation in the shared memory mode.

SMAM

Shared Memory Address Match Input

This pin indicates an access to shared memory when

active. The type of access is decided by MEMR or

MEMW.

SROE

Static RAM Output Enable

Output

This pin directly controls the external SRAM’s OE pin.

SRCS/IRQ12

Static RAM Chip Select

Output

This pin directly controls the external SRAM’s chip se-

lect (CS) pin when the Flash boot ROM option is

selected.

When Flash boot ROM option is not selected, this pin

becomes IRQ12.

SRWE/WE

Static RAM Write Enable/

Write Enable

Output

This pin (SRWE) directly controls the external SRAM’s

WE pin when a Flash memory device is not

implemented.

When a Flash memory device is implemented, this pin

becomes a global write enable (WE) pin.

XTAL1

Crystal Connection

Input

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. Alternatively, an

external 20 MHz CMOS-compatible clock signal can be

used to drive this pin. Refer to the section on External

Crystal Characteristics for more details.

XTAL2

Crystal Connection

Output

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. If an external

clock is used, this pin should be left unconnected.

Am79C961

1-501

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