7), which is hardwired to ONE. The PCnet-PCI II con-
troller is capable of detecting an I/O or a memory
mapped I/O cycle even when its address phase imme-
diately follows the data phase of a transaction to a dif-
ferent target, without any idle state in-between. There
will be no contention on the DEVSEL, TRDY and STOP
signals, since the PCnet-PCI II controller asserts
DEVSEL on the second clock after FRAME is asserted
(medium timing).
CLK
1
2
3
4
5
6
7
8
9
10
11
FRAME
AD
ADDR
DATA
C/BE
0010
BE
PAR
PAR
PAR
IRDY
TRDY
DEVSEL
STOP
Figure 3. Slave Read Using I/O Command
19436C-6
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Am79C970A