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AM79C970A

PCnet™-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product

Advanced Micro Devices 

CLK

1

2

3

4

5

6

7

8

9

10

11

FRAME

AD

ADDR

DATA

C/BE

0111

BE

PAR

PAR

PAR

IRDY

TRDY

DEVSEL

STOP

Figure 4. Slave Write Using Memory Command

19436C-7

Expansion ROM Transfers

The host must initialize the Expansion ROM Base Ad-

dress register at offset 30h in the PCI configuration

space with a valid address before enabling the access

to the device. The base address must be aligned to a

64K boundary as indicated by ROMSIZE (PCI Expan-

sion ROM Base Address register, bits 15–11). The PC-

net-PCI II controller will not react to any access to the

Expansion ROM until both MEMEN (PCI Command

register, bit 1) and ROMEN (PCI Expansion ROM Base

Address register, bit 0) are set to ONE. After the Expan-

sion ROM is enabled, the PCnet-PCI II controller will

assert DEVSEL on all memory read accesses with an

address between ROMBASE and ROMBASE + 64K –

4. The PCnet-PCI II controller aliases all accesses to

the Expansion ROM of the command types ‘‘Memory

Read Multiple’’ and ‘‘Memory Read Line’’ to the basic

Memory Read command. Eight-bit, 16-bit and 32-bit

read transfers are supported.

Since setting MEMEN also enables memory mapped

access to the I/O resources, attention must be given

the PCI Memory Mapped I/O Base Address register,

before enabling access to the Expansion ROM. The

host must set the PCI Memory Mapped I/O Base Ad-

dress register to a value that prevents the PCnet-PCI II

controller from claiming any memory cycles not in-

tended for it.

The PCnet-PCI II controller will always read four bytes

for every host Expansion ROM read access. TRDY will

not be asserted until all four bytes are loaded into an in-

ternal scratch register. The cycle TRDY is asserted de-

pends on the programming of the Expansion ROM

interface timing. The following figure assumes that

ROMTMG (BCR18, bits 15–12) is at its default value.

Since the target latency for the Expansion ROM access

is considerably long, the PCnet-PCI II controller dis-

connects at the second data phase, when the host tries

do to perform a burst read operation of the Expansion

ROM. This behavior complies with the requirements for

latency issues in the PCI environment and allows other

devices to get fair access to the bus.

When the host tries to write to the Expansion ROM, the

PCnet-PCI II controller will claim the cycle by asserting

DEVSEL. TRDY will be asserted one clock cycle later.

The write operation will have no effect.

The PCnet-PCI II controller supports fast back-to-back

transactions to different targets. This is indicated by the

Am79C970A

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