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AM79C970A

PCnet™-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product

Advanced Micro Devices 

Fast Back-To-Back Capable bit (PCI Status register, bit

7), which is hardwired to ONE. The PCnet-PCI II con-

troller is capable of detecting a memory cycle even

when its address phase immediately follows the data

phase of a transaction to a different target without any

idle state in-between. There will be no contention on

the DEVSEL, TRDY and STOP signals, since the PC-

net-PCI II controller asserts DEVSEL on the second

clock after FRAME is asserted (medium timing).

CLK

1

2

3

4

5

FRAME

AD

ADDR

C/BE

CMD

BE

PAR

PAR

IRDY

TRDY

DEVSEL

STOP

42

43

44

45

DATA

PAR

DEVSEL is sampled

Figure 5. Expansion ROM Read

19436C-8

Exclusive Access

The host can lock a set of transactions to the PC-

net-PCI II controller. The lock allows exclusive access

to the device and can be used to guarantee atomic op-

erations. The PCnet-PCI II controller transitions from

the unlocked to the locked state when LOCK is deas-

serted during the address phase of a transaction that

selects the device as the target. The controller stays in

the locked state until both FRAME and LOCK are deas-

serted, or until the device signals a target abort. Note

that this protocol means the device locks itself on any

normal transaction. The controller will unlock automat-

ically at the end of a normal transaction, because

FRAME and LOCK will be deasserted. The lock spans

over the whole slave address space. The lock only ap-

plies to slave accesses. The PCnet-PCI II controller

might perform bus master cycles while being locked in

slave mode. When another master tries to access the

PCnet-PCI II controller while it is in the locked state, the

device terminates the access with a disconnect/retry

sequence.

Slave Cycle Termination

There are three scenarios besides normal completion

of a transaction where the PCnet-PCI II controller is the

target of a slave cycle and it will terminate the access.

Disconnect When Busy

The PCnet-PCI II controller cannot service any slave

access while it is reading the contents of the Microwire

EEPROM. Simultaneous access is not possible to

avoid conflicts, since the Microwire EEPROM is used

to initialize some of the PCI configuration space loca-

tions and most of the BCRs. The Microwire EEPROM

30

Am79C970A

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