CY7C1049D Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1049D Datasheet PDF : 12 Pages
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CY7C1049D
Switching Characteristics[5] Over the Operating Range
Parameter
Description
Read Cycle
tpower
VCC(typical) to the First Access[6]
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low Z[8]
OE HIGH to High Z[7, 8]
CE LOW to Low Z[8]
CE HIGH to High Z[7, 8]
tPU
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
Write Cycle[9, 10]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[8]
WE LOW to High Z[7, 8]
-10
Min.
Max.
Unit
100
–
μs
10
–
ns
–
10
ns
3
–
ns
–
10
ns
–
5
ns
0
–
ns
–
5
ns
3
–
ns
–
5
ns
0
–
ns
–
10
ns
10
–
ns
7
–
ns
7
–
ns
0
–
ns
0
–
ns
7
–
ns
6
–
ns
0
–
ns
3
–
ns
–
5
ns
Data Retention Characteristics Over the Operating Range
Parameter
Description
Conditions[12]
VDR
ICCDR
tCDR[3]
tR[11]
VCC for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
VCC = VDR = 2.0 V,
CE > VCC – 0.3 V
VIN > VCC – 0.3 V or VIN < 0.3 V
Min. Max Unit
2.0
–
V
–
10
mA
0
–
ns
tRC
–
ns
Notes
4. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the
test load shown in Figure (c)
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH
and 30-pF load capacitance.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals
can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05474 Rev. *E
Page 5 of 12
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