CY7C1049D Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C1049D

4-Mbit (512 K × 8) Static RAM

Cypress Semiconductor 

CY7C1049D

Switching Waveforms(continued)

Figure 2. Read Cycle No. 2 (OE Controlled)[14, 15]

ADDRESS

tRC

CE

OE

DATA OUT

VCC

SUPPLY

CURRENT

ADDRESS

CE

WE

DATA I/O

tACE

tDOE

tLZOE

HIGH IMPEDANCE

tLZCE

tPU

50%

DATA VALID

tHZOE

tHZCE

HIGH

IMPEDANCE

tPD

ICC

50%

ISB

Figure 3. Write Cycle No. 1 (CE Controlled)[16, 17]

tWC

tSCE

tSA

tSCE

tAW

tHA

tPWE

tSD

tHD

DATA VALID

Notes

15. Address valid prior to or coincident with CE transition LOW.

16. Data I/O is high impedance if OE = VIH.

17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.

Document #: 38-05474 Rev. *E

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