CY7C1049D Ver la hoja de datos (PDF) - Cypress Semiconductor

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Lista de partido

CY7C1049D

4-Mbit (512 K × 8) Static RAM

Cypress Semiconductor 

CY7C1049D

Data Retention Waveform

VCC

4.5 V

tCDR

CE

DATA RETENTION MODE

VDR > 2 V

4.5 V

tR

Switching Waveforms

Figure 1. Read Cycle No. 1[13, 14]

tRC

ADDRESS

DATA OUT

tAA

tOHA

PREVIOUS DATA VALID

DATA VALID

Notes

11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 μs or stable at VCC(min.) > 50 μs

12. No input may exceed VCC + 0.5 V.

13. Device is continuously selected. OE, CE = VIL.

14. WE is HIGH for read cycle.

Document #: 38-05474 Rev. *E

Page 6 of 12

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