DM9102F Ver la hoja de datos (PDF) - Unspecified

Número de pieza

componentes Descripción

Lista de partido

DM9102F

10/100Mbps Single Chip LAN Controller

Unspecified 

T Register Definition

a PCI Configuration Registers

The definitions of PCI Configuration Registers are

based on the PCI specification revision 2.1 and

provides the initialization and configuration

information to operate the PCI interface in the

DM9102. All registers can be accessed with byte,

DM9102

10/100Mbps Single Chip LAN Controller

word, or double word mode. As defined in PCI

specification 2.1, read accesses to reserve or

unimplemented registers will return a value of “0.”

These registers are to be described in the following

sections.

PCI Configuration Registers Mapping :

Description

Identifier

Identification

PCIID

Command & Status

PCICS

Revision

PCIRV

Miscellaneous

PCILT

I/O Base Address

PCIIO

Memory Base Address

PCIMEM

Reserved

--------

Subsystem Identification

PCISID

Expansion ROM Base Address

PCIROM

Capability Pointer

CAP_PTR

Reserved

--------

Interrupt & Latency

PCIINT

Device Specific Configuration Register PCIUSR

Address Offset

00H

04H

08H

0CH

10H

14H

18H - 28H

2CH

30H

34H

38H

3CH

40H

Value of Reset

91021282H

02900007H

02000020H

00000000H

undefined

undefined

load from SROM

00000000H

00000050H

281401XXH

00000000H

12

Final

Version: DM9102-DS-F03

August 30, 2000

Share Link: