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DM9102F

10/100Mbps Single Chip LAN Controller

Unspecified 

Capabilities Pointer (Xxxxxx34 - Cap _Ptr)

Cap_Ptr

0 1 0 1 0 0 0 0 Offset 34H

7

0

DM9102

10/100Mbps Single Chip LAN Controller

Bit

Default

31:8 000000h

7:0 01010000b

Type

RO

RO

Description

Reserved

Capability Pointer

The Cap_Ptr provides an offset (default is 50h) into the function’s PCI Configuration

Space for the location of the first term in the Capabilities Linked List. The Cap_Ptr

offset is DOUBLE WORD aligned so the two least significant bits significant bits are

always “0”s

Interrupt & Latency Configuration (Xxxxxx3c - PCIINT)

31

24 23

16 15

MAX_LAT

Maximum Latency Timer

Minimum Grant

Interrupt Pin

Interrupt Line

MIN_GNT

INT_PIN

87

0

INT_LINE

Bit

31:24

23:16

15:8

7:0

Default

28h

14h

01h

XXh

Type

RO

RO

RO

RO

Description

Maximum Latency Timer that can be sustained (Read Only and Read As

28h)

Minimum Grant

Minimum Length of a Burst Period (Read Only and Read As 14h)

Interrupt Pin read as 01h to indicate INTA#

Interrupt Line that Is Routed to the Interrupt Controller

Device Specific Configuration Register (Xxxxxx40 - PCIUSR)

31 30 29 28 27 26 25 24 23

16 15

87

0

Reserved

Device Specific

Device Specific

20

Final

Version: DM9102-DS-F03

August 30, 2000

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