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DM9102F

10/100Mbps Single Chip LAN Controller

Unspecified 

Bit

Default

31

0b

30

0b

29

0b

28

0b

27

0b

26:25

01b

24

0b

23

1b

22

0b

21

0b

20

1b

19:16

0000b

Type

R/C

R/C

R/C

R/C

R/C

R/C

R/C

R/C

R/C

R/C

R/C

RO

DM9102

10/100Mbps Single Chip LAN Controller

Description

Detected Parity Error

The DM9102 samples the AD[0:31], C/BE[0:3]#, and the PAR

signal to check parity and to set parity errors. In slave mode,

the parity check falls on command phase and data valid phase

(IRDY# and TRDY# both active). While in master mode, the

DM9102 will check during each data phase of a memory read

cycle for a parity error During a memory write cycle, if an error

occurs, the PERR# signal will be driven by the target. This bit

is set by the DM9102 and cleared by writing "1". There is no

effect by writing "0".

Signal For System Error

This bit is set when the SERR# signal is driven by the DM9102.

This system error occurs when an address parity is detected

under the condition that bit 8 and bit 6 in command register

below are set.

Master Abort Detected

This bit is set when the DM9102 terminates a master cycle with

the master-abort bus transaction.

Target Abort Detected

This bit is set when the DM9102 terminates a master cycle due

to a target-abort signal from other targets.

Send Target Abort (0 For No Implementation)

The DM9102 will never assert the target-abort sequence.

DEVSEL Timing (01 Select Medium Timing)

Medium timing of DEVSEL# means the DM9102 will assert

DEVSEL# signal two clocks after FRAME# is sample

“asserted.”

Data Parity Error Detected

This bit will take effect only when operating as a master and

when a Parity Error Response Bit in command configuration

register is set. It is set under two conditions:

(i) PERR# asserted by the DM9102 in memory data read error,

(ii) PERR# sent from the target due to memory data write error.

Slave mode Fast Back-To-Back Capable (1 For Good

Capability)

This bit is always reads "1" to indicate that the DM9102 is

capable of accepting fast back-to-back transaction as a slave

mode device.

User-Definable-Feature Supported (0 For No Support)

66 MHz Capable (0 For No Capability)

New Capabilities

This bit indicates whether this function implements a list of extended

capabilities such as PCI power management. When set this bit

indicates the presence of New Capabilities. A value of 0 means that

this function does not implement New Capabilities.

Reserved

Final

15

Version: DM9102-DS-F3

August 30, 2000

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