DM9102F Ver la hoja de datos (PDF) - Unspecified
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DM9102F Datasheet PDF : 63 Pages
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Command Register Definition:
DM9102
10/100Mbps Single Chip LAN Controller
15
10 9
8
7
6
5
4
3
2
1
0
Reserved
0 R/W 0 R/W 0
0
0 R/W R/W R/W
Mast Mode Fast Back-To-Back
SERR# Driver Enable/Disable
Address/Data Steeping
Parity Error Response Enable/Disable
VGA Palette snoop
Memory Write and Invalid
Special Cycle
Master Device Capability Enable/Disable
Memory Space Access Enable/Disable
I/O Space Access Enable/Disable
Bit
15:10
9
Default
000000b
0b
8
0b
7
0b
6
0b
5
0b
4
0b
3
0b
2
1b
1
1b
0
1b
Type
RO
RO
RW
RO
RW
RO
RO
RO
RW
RW
RW
Description
Reserved
Master Mode Fast Back-To-Back (0 For No Support)
The DM9102 does not support master mode fast back-to-back capability
and will not generate fast back-to-back cycles.
SERR# Driver Enable/Disable
This bit controls the assertion of SERR# signal output. The SERR# output
will be asserted on detection of an address parity error and if both this bit
and bit 6 are set.
Address/Data Stepping (0 For No Stepping)
Parity Error Response Enable/Disable
Setting this bit will enable the DM9102 to assert PERR# on the detection of
a data parity error and to assert SERR# for reporting address parity error.
VGA Palette Snooping (0 For No Support)
Memory Write and Invalid (0 For No Implementation)
The DM9102 only generates Memory write cycle.
Special Cycles (0 For No Implementation)
Master Device Capability Enable/Disable
When this bit is set, DM9102 has the ability of master mode operation.
Memory Space Access Enable/Disable
This bit controls the ability of memory space access. The memory access
includes memory mapped I/O access and Boot ROM access. As the system
boots up, this bit will be enabled by BIOS for Boot ROM memory access.
While in normal operation using memory mapped I/O access, this bit should
be set by driver before memory access cycles.
I/O Space Access Enable/Disable
This bit controls the ability of I/O space access. It will be set by BIOS after
power on.
16
Final
Version: DM9102-DS-F03
August 30, 2000
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