DM9102H Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.
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DM9102H Datasheet PDF : 77 Pages
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DM9102H
Single Chip Fast Ethernet NIC Controller
6. Register Definition
6.1 PCI Configuration Registers
The definitions of PCI Configuration Registers are based on
the PCI specification revision 2.2 and it provides the
initialization and configuration information to operate the PCI
interface in the DM9102H. All registers can be accessed
with byte, word, or double word mode. As defined in PCI
specification 2.1, read accesses to reserve or
unimplemented registers will return a value of “0.” These
registers are to be described in the following sections.
The default value of PCI configuration registers after reset.
Description
Identifier
Identification
PCIID
Command & Status
PCICS
Revision
PCIRV
Miscellaneous
PCILT
I/O Base Address
PCIIO
Memory Base Address
PCIMEM
Reserved
--------
Reserved
--------
Subsystem Identification
PCISID
Expansion ROM Base Address
PCIROM
Capability Pointer
CAP_PTR
Reserved
--------
Interrupt & Latency
PCIINT
Device Specific Configuration Register PCIUSR
Power Management Register
PCIPMR
Power Management Control & Status PMCSR
* It is written to 02100007H by most BIOS.
** It may be changed from EEPROM in application.
Address Offset
00H
04H
08H
0CH
10H
14H
18H - 28H
24H
2CH
30H
34H
38H
3CH
40H
50H
54H
Value of Reset
91021282H
02100000H*
02000060H
BIOS determine
System allocate
System allocate
00000000H
00000000H
load from SROM
00000000H
00000050H
00000000H
System allocate bit7~0
00000000H**
C0310001H**
00000100H
Key to Default
In the register description that follows, the default column
takes the form <Reset Value>
Where：
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
<Access Type>:
RO = Read only
RW = Read/Write
R/C: means Read / Write & Write "1" for Clear.
Final
8
Version: DM9102H-12-DS-F01
February 15, 2008
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