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DM9102H

Single Chip Fast Ethernet NIC Controller

Davicom Semiconductor, Inc. 

DM9102H

Single Chip Fast Ethernet NIC Controller

6.1.8 Expansion ROM Base Address (xxxxxx30 - PCIROM)

31

ROM Base Address

ROM Base Address

18 17

10 9

10

000000000000000

Reserved

R/W

Bit

31:10

Default

00H

9:1 000000000

0

0

Type

RW

RO

RW

Description

ROM Base Address With 256K Boundary

PCIROM bit17~10 are hardwired to 0, indicating ROM Size is up to 256K Size

Reserved Bits Read As 0

Expansion ROM Decoder Enable/Disable

If this bit and the memory space access bit are both set to 1, the DM9102H will

respond to its expansion ROM

6.1.9 Capabilities Pointer (xxxxxx34H - Cap _Ptr)

31

Reserved

Capability Pointer

87

0

01 01 0 0 0 0

Bit

Default

31:8 000000H

7:0 01010000

Type

RO

RO

Description

Reserved

Capability Pointer

The Cap_ Ptr provides an offset (default is 50H) into the function’s PCI

Configuration Space for the location of the first term in the Capabilities Linked List.

The Cap_ Ptr offset is double word aligned so the two least significant bits are

always “0”s

Final

14

Version: DM9102H-12-DS-F01

February 15, 2008

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