DM9102H Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.

Número de pieza

componentes Descripción

Lista de partido

DM9102H

Single Chip Fast Ethernet NIC Controller

Davicom Semiconductor, Inc. 

DM9102H

Single Chip Fast Ethernet NIC Controller

6.2.1 System Control Register (CR0)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

31:26

25:24

23

Name

Reserved

Reserved

TBURST

22 RBURST

21

MRM

20:1 Reserved

0

SR

Default

DEH,RO

00,RO

0,RW

0,RW

0,RW

0,RO

0,RW

Description

Reserved

Reserved

TX DESC Burst Mode

When set, PCI access TX DESC in burst mode

RX DESC Burst Mode

When set, PCI access RX DESC in burst mode

Memory Read Multiple

When set, the DM9102H will use memory read multiple command (C/BE3~0 1100)

when it initialize the memory read burst transaction as a master device

When reset, it will use memory read command (C/BE3 ~ 0 = 0110) for the same

master operation

Reserved

Software Reset

When set, the DM9102H will make an internal reset cycle. All consequent action to

DM9102H should wait at least 32 PCI clock cycles to start and no necessary to

reset this bit

6.2.2 Transmit Descriptor Poll Demand (CR1)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

Name

Default

Description

31:0

TDP FFFFFFFFH Transmit Descriptor Polling Command

,WO

Writing any value to this port will force DM9102H to poll the transmit descriptor. If

the acting descriptor is not available, transmit process will return to suspend state.

If the descriptor shows buffer available, transmit process will begin the data

transfer

6.2.3 Receive Descriptor Poll Demand (CR2)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Final

19

Version: DM9102H-12-DS-F01

February 15, 2008

Share Link: