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DM9102H

Single Chip Fast Ethernet NIC Controller

Davicom Semiconductor, Inc. 

DM9102H

Single Chip Fast Ethernet NIC Controller

Bit

Name

Default

Description

31:0

RDP FFFFFFFFH Receive Descriptor Polling Command

,WO

Writing any value to this port will force DM9102H to poll the receive descriptor. If

the acting descriptor is not available, receive process will return to suspend state.

If the descriptor shows buffer available, receive process will begin the data transfer

6.2.4 Receive Descriptor Base Address (CR3)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00 00

Bit

Name

Default

Description

31:0 RDBA 00000000H, Receive Descriptor Base Address

RW

This register defines base address of receive descriptor-chain. The receive

descriptor- polling command, after CR3 is set, will make DM9102H to fetch the

descriptor at the Base-Address

This is a working register, so the value of reading is unpredictable

6.2.5 Transmit Descriptor Base Address (CR4)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

00 00

Bit

Name

Default

Description

31:0 TDBA 00000000H, Transmit Descriptor Base Address

RW

This register defines base address of transmit descriptor-chain. The transmit

descriptor- polling command after CR4 is set to make DM9102H fetch the

descriptor at the Base-Address

This is a working register, so the value of reading is unpredictable

6.2.6 Network Status Report Register (CR5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Note: Bits [13:0] can be cleared by written 1 to them respectively.

Bit

Name

Default

Description

31:26 Reserved 000000,RO Reserved

25:23 SBEB

000,RO System Bus Error Bits

These bits are read only and used to indicate the type of system bus fatal error. Valid

only when System Bus Error is set. The mapping bits are shown below

Bit25 Bit24 Bit23 Bus Error Type

Final

20

Version: DM9102H-12-DS-F01

February 15, 2008

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