DM9102H Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.

Número de pieza

componentes Descripción

Lista de partido

DM9102H

Single Chip Fast Ethernet NIC Controller

Davicom Semiconductor, Inc. 

9

FDM

8 Reserved

7

PAM

6

PM

5:4 Reserved

3

PBF

2

HOFM

1

RXRC

0

HPFM

0,RW

0,RO

0,RW

0,RW

0,RO

0,RW

0,RO

0,RW

0,RO

DM9102H

Single Chip Fast Ethernet NIC Controller

Full-duplex Mode

When internal PHY is selected, this bit is the status of full-duplex mode of internal

PHY

When external PHY is selected, set this bit to make the DM9102H operate in the

full-duplex mode

Must be Zero

Pass All Multicast

When set, any packet with a multicast destination address is received by the

DM9102H. The packet with a physical address will also be filtered based on the

filter mode setting

Promiscuous Mode

When set, any incoming valid frame is received by the DM9102H, and no matter

what the destination address is. The DM9102H is initialized to this mode after reset

operation

Must be Zero

Pass Bad Frame

When set, the DM9102 is indicated that receiving the bad frames, including runt

packets and truncated frames, is caused by the FIFO overflow. The bad frame also

has to pass the address filtering if the DM9102H is not set in promiscuous mode

Hash-only Filter Mode

This is a read-only bit and mapped from the set-up frame together with bit4,0 of

CR6

It is set to indicate the DM9102H operate in a Hash-only Filtering Mode

Receive Start/Stop Command

When set, receive process will begin by fetching the receive descriptor for available

buffer to store the new-coming packet (placed in the running state). If the fetched

descriptor is owned by the host (no descriptor is owned by the DM9102H), the

receive process will enter the suspend state and receive buffer unavailable

CR5<7> sets. Otherwise it runs to wait for the packet’s income. When reset,

receive process is placed in the stopped state after completing the reception of the

current frame

Hash/Perfect Filter Mode

This is a read only bit and mapped from the setup frame together with CR6<4>,

and CR6<2>. When reset, the DM9102H does a perfect address filter of incoming

frames according to the addresses specified in the setup frame. When set, the

DM9102H does an imperfect address filtering for the incoming frame with a

multicast address according to the hash table specified in the setup frame. The

filtering mode (perfect / imperfect) for the frame with a physical address will depend

on CR6<2>.

6.2.8 Interrupt Mask Register (CR7)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Final

24

Version: DM9102H-12-DS-F01

February 15, 2008

Share Link: