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AN-6921

Integrated Critical Mode PFC / Quasi-Resonant Current Mode PWM Controller FAN6921

Fairchild Semiconductor 

AN-6921

Part B. DC/DC Section

[STEP-B1] Determine the Reflected Output Voltage

(VRO)

Figure 11 shows the typical operation waveforms of a quasi-

resonant flyback converter. When the MOSFET is turned

off, the input voltage (PFC output voltage), together with

the output voltage reflected to the primary (VRO), is imposed

on the MOSFET. When the MOSFET is turned on, the sum

of input voltage reflected to the secondary side and the

output voltage is applied across the diode. Thus, the

maximum nominal voltage across the MOSFET (Vdsnom) and

diode are given as:

V nom

DS

= VO.PFC.H

+ n(VO

+ VF )

= VO.PFC.H

+ VRO

where:

(20)

n = VRO

VO + VF

V nom

D

= VO

+ VO.PFC.H

n

= VO

+

VO.PFC .H

VRO

(VO + VF )

(21)

By increasing VRO (i.e. the turns ratio, n), the capacitive

switching loss and conduction loss of the MOSFET are

reduced. This also reduces the voltage stress of the

secondary-side rectifier diode. However, this increases the

voltage stress on the MOSFET. Therefore, VRO should be

determined by a trade-off between the voltage stresses of the

MOSFET and diode. It is typical to set VRO such that VDSnorm

and VDnom are 75~85% of their voltage ratings.

APPLICATION NOTE

(Design Example) Assuming 650V MOSFET and

100V MOSFET are used for primary side and

secondary side, respectively, with 18% voltage

margin:

0.82 ⋅ 650V > VDS nom = VO.PFC + VRO

∴VRO < 0.82 ⋅ 650 −VO.PFC = 133V

0.82 ⋅100

> VD nom

= VO

+

VO . PFC

VRO

(VO

+ VF )

∴VRO

> VD nom

=

VO . PFC

0.82 ⋅100 − VO

(VO

+ VF )

= 121V

VRO is determined as 130V.

[STEP-B2] Transformer Design

Figure 12 shows the typical switching timing of a quasi-

resonant converter. The sum of MOSFET conduction time

(tON), diode conduction time (tD), and drain voltage falling

time (tF) is the switching period (tS). To determine the

primary-side inductance (Lm), the following parameters

should be determined first.

Minimum Switching Frequency (fS.QRmin)

The minimum switching frequency occurs at the minimum

input voltage and full-load condition, which should be

higher than 20kHz to avoid audible noise. By increasing

fS.QRmin, the transformer size can be reduced. However, this

results in increased switching losses. Determine fS.QRmin by a

trade-off between switching losses and transformer size.

Typically fS.QRmin is set to around 50kHz.

Falling Time of the MOSFET Drain Voltage (tF)

As shown in Figure 12, the MOSFET drain voltage fall time

is half of the resonant period of the MOSFET’s effective

output capacitance and primary-side inductance. The typical

value for tF is 0.6~1.2µs.

Non-Conduction Time of the MOSFET (tOFF) FAN6921

has a minimum non-conduction time of MOSFET (8µs),

during which turning on of MOSFET is prohibited. To

maximize the efficiency, it is necessary to turn on the

MOSFET at the first valley of MOSFET drain-to-source

voltage at heavy-load condition. Therefore, the MOSFET

non-conduction time at heavy load condition should be

larger than 8µs.

After determining fS.QRmin and tF, the maximum duty cycle is

calculated as:

Dmax

=

VRO

VRO

+ VO.PFC.L

⋅ (1−

f min

S .QR

⋅tF )

(22)

Then, the primary-side inductance is obtained as:

Lm

=

ηQR ⋅ (VO.PFC.L ⋅ Dmax )2

2⋅

f P min

S .QR

OUT

(23)

Figure 11. Typical Waveforms of QR Flyback Converter

© 2010 Fairchild Semiconductor Corporation

Rev. 1.0.1 • 8/24/10

8

www.fairchildsemi.com

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