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IDT70P35 Ver la hoja de datos (PDF) - Integrated Device Technology

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IDT70P35 Datasheet PDF : 22 Pages
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IDT70P35/34L (IDT70T25/24L)
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
ADVANCED
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70P35/34L20
(70P25/24L20)
Com'l Only
70P35/34L25
(70P25/24L25)
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
20
____
25
____
ns
tAA
Address Access Time
____
20
____
25
ns
tACE
Chip Enable Access Time(3)
____
20
____
25
ns
tABE
Byte Enable Access Time(3)
____
20
____
25
ns
tAOE
Output Enable Access Time(3)
____
12
____
13
ns
tOH
Output Hold from Address Change
3
____
3
____
ns
tLZ
Output Low-Z Time(1,2)
3
____
3
____
ns
tHZ
Output High-Z Time(1,2)
____
12
____
15
ns
tPU
Chip Enable to Power Up Time(1,2)
0
____
0
____
ns
tPD
Chip Disable to Power Down Time(1,2)
tSOP
Semaphore Flag Update Pulse (OE or SEM)
____
20
____
25
ns
10
____
10
____
ns
tSAA
Semaphore Address Access(3)
____
20
____
25
ns
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL.
5683 tbl 11
Waveform of Read Cycles(5)
tRC
ADDR
CE
tAA (4)
tACE (4)
tAOE (4)
OE
UB, LB
tABE(4)
R/W
DATAOUT
BUSYOUT
tLZ (1)
VALID DATA(4)
tBDD (3,4)
tOH
tHZ(2)
,
5683 drw 09
NOTES:
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
61.412

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