IDT70P35 Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT70P35
Integrated Device Technology
IDT70P35 Datasheet PDF : 22 Pages
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IDT70P35/34L (IDT70T25/24L)
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
ADVANCED
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70P35/34L20
(70P25/24L20)
Com'l Only
70P35/34L25
(70P25/24L25)
Com'l
& Ind
Symbol
BUSY TIMING (M/S = VIH)
Parameter
Min.
Max.
Min.
Max. Unit
tBAA
BUSY Access Time from Address Match
____
20
____
20
ns
tBDA
BUSY Disable Time from Address Not Matched
____
20
____
20
ns
tBAC
BUSY Access Time from Chip Enable LOW
____
20
____
20
ns
tBDC
BUSY Disable Time from Chip Enable HIGH
____
17
____
17
ns
tAPS
Arbitration Priority Set-up Time (2)
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data(3)
____
30
____
30
ns
tWH
Write Hold After BUSY(5)
BUSY TIMING (M/S = VIL)
15
____
17
____
ns
tWB
BUSY Input to Write(4)
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
15
____
17
____
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
____
45
____
50
ns
tDDD
Write Data Valid to Read Data Delay(1)
____
35
____
35
ns
NOTES:
5683 tbl 13
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND
BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
Timing Waveform of Write Port-to-Port Read and BUSY(2,4,5) (M/S = VIH)
tWC
ADDR"A"
R/W"A"
MATCH
tWP
tDW
tDH
DATAIN "A"
tAPS(1)
VALID
ADDR"B"
BUSY"B"
tBAA
MATCH
tBDA
tBDD
tWDD
DATAOUT "B"
tDDD(3)
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for both left and right ports. Port “A” may be either the left or right port. Port “B ” is the port opposite from port “A”.
VALID
,
5683 drw 14
61.452
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