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IDT70P35

HIGH-SPEED 1.8V 8/4K x 18 DUAL-PORT 8/4K x 16 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT70P35/34L(IDT70P25/24L)

High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM

ADVANCED

Industrial and Commercial Temperature Ranges

to inhibit the other from accessing a portion of the Dual-Port SRAM or any

other shared resource.

The Dual-Port SRAM features a fast access time, and both ports are

completely independent of each other. This means that the activity on the

left port in no way slows the access time of the right port. Both ports are

identical in function to standard CMOS Static RAM and can be accessed

at the same time with the only possible conflict arising from the simultaneous

writing of, or a simultaneous READ/WRITE of, a non-semaphore location.

Semaphores are protected against such ambiguous situations and may

be used by the system program to avoid any conflicts in the non-

semaphore portion of the Dual-Port SRAM. These devices have an

automatic power-down feature controlled by CE, the Dual-Port SRAM

enable, and SEM, the semaphore enable. The CE and SEM pins control

on-chip power down circuitry that permits the respective port to go into

standby mode when not selected. This is the condition which is shown in

Truth Table I where CE and SEM are both HIGH.

Systems which can best use the IDT70P35/34L (IDT70P25/24L)

contain multiple processors or controllers and are typically very high-

speed systems which are software controlled or software intensive. These

systems can benefit from a performance increase offered by the IDT70P35/

34L (IDT70P25/24L)'s hardware semaphores, which provide a lockout

mechanism without requiring complex programming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in

varying configurations. The IDT70P35/34L (IDT70P25/24L) does not

use its semaphore flags to control any resources through hardware, thus

allowing the system designer total flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred

in either processor. This can prove to be a major advantage in very

high-speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are indepen-

dent of the Dual-Port SRAM. These latches can be used to pass a flag,

or token, from one port to the other to indicate that a shared resource

is in use. The semaphores provide a hardware assist for a use

assignment method called “Token Passing Allocation.” In this method,

the state of a semaphore latch is used as a token indicating that shared

resource is in use. If the left processor wants to use this resource, it

requests the token by setting the latch. This processor then verifies its

success in setting the latch by reading it. If it was successful, it

proceeds to assume control over the shared resource. If it was not

successful in setting the latch, it determines that the right side

processor has set the latch first, has the token and is using the shared

resource. The left processor can then either repeatedly request that

semaphore’s status or remove its request for that semaphore to

perform another task and occasionally attempt again to gain control of

the token via the set and test sequence. Once the right side has

relinquished the token, the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by

writing a zero into a semaphore latch and is released when the same

side writes a one to that latch.

The eight semaphore flags reside within the IDT70P35/34L

(IDT70P25/24L) in a separate memory space from the Dual-Port

SRAM. This address space is accessed by placing a LOW input on

the SEM pin (which acts as a chip select for the semaphore flags) and

using the other control pins (Address, OE, and R/W) as they would be

used in accessing a standard static RAM. Each of the flags has a

unique address which can be accessed by either side through

address pins A0 – A2. When accessing the semaphores, none of the

other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If a LOW level

is written into an unused semaphore location, that flag will be set to a zero

on that side and a one on the other side (see Truth Table V). That

semaphore can now only be modified by the side showing the zero. When

a one is written into the same location from the same side, the flag will be

set to a one for both sides (unless a semaphore request from the other side

is pending) and then can be written to by both sides. The fact that the side

which is able to write a zero into a semaphore subsequently locks out writes

from the other side is what makes semaphore flags useful in interprocessor

communications. (A thorough discussion on the use of this feature follows

shortly.) A zero written into the same location from the other side will be

stored in the semaphore request latch for that side until the semaphore is

freed by the first side.

When a semaphore flag is read, its value is spread into all data bits so

that a flag that is a one reads as a one in all data bits and a flag containing

a zero reads as all zeros. The read value is latched into one side’s output

register when that side's semaphore select (SEM) and output enable (OE)

signals go active. This serves to disallow the semaphore from changing

state in the middle of a read cycle due to a write cycle from the other side.

Because of this latch, a repeated read of a semaphore in a test loop must

cause either signal (SEM or OE) to go inactive or the output will never

change.

A sequence WRITE/READ must be used by the semaphore in

order to guarantee that no system level contention will occur. A

processor requests access to shared resources by attempting to write

a zero into a semaphore location. If the semaphore is already in use,

the semaphore request latch will contain a zero, yet the semaphore

flag will appear as one, a fact which the processor will verify by the

subsequent read (see Truth Table V). As an example, assume a

processor writes a zero to the left port at a free semaphore location. On

a subsequent read, the processor will verify that it has written success-

fully to that location and will assume control over the resource in

question. Meanwhile, if a processor on the right side attempts to write

a zero to the same semaphore flag it will fail, as will be verified by the

fact that a one will be read from that semaphore on the right side during

subsequent read. Had a sequence of READ/WRITE been used

instead, system contention problems could have occurred during the

gap between the read and write cycles.

It is important to note that a failed semaphore request must be

followed by either repeated reads or by writing a one into the same

location. The reason for this is easily understood by looking at the

simple logic diagram of the semaphore flag in Figure 4. Two sema-

phore request latches feed into a semaphore flag. Whichever latch is

first to present a zero to the semaphore flag will force its side of the

semaphore flag LOW and the other side HIGH. This condition will

continue until a one is written to the same semaphore request latch.

Should the other side’s semaphore request latch have been written to

a zero in the meantime, the semaphore flag will flip over to the other side

as soon as a one is written into the first side’s request latch. The second

side’s flag will now stay LOW until its semaphore request latch is written to

6.2402

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