IDT70P35 Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT70P35
Integrated Device Technology
IDT70P35 Datasheet PDF : 22 Pages
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IDT70P35/34L(IDT70P25/24L)
High-Speed 1.8V 8/4K x 18 (8/4K x 16) Dual-Port Static RAM
ADVANCED
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
70P35/34L20
(70P25/24L20)
Com'l Only
70P35/34L25
(70P25/24L25)
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tWC
Write Cycle Time
20
____
25
____
ns
tEW
Chip Enable to End-of-Write(3)
15
____
20
____
ns
tAW
Address Valid to End-of-Write
tAS
Address Set-up Time(3)
15
____
20
____
ns
0
____
0
____
ns
tWP
Write Pulse Width
15
____
20
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
15
____
15
____
ns
tHZ
Output High-Z Time(1,2)
tDH
Data Hold Time(4)
tWZ
Write Enable to Output in High-Z(1,2)
tOW
Output Active from End-of-Write(1,2,4)
____
12
____
15
ns
0
____
0
____
ns
____
12
____
15
ns
0
____
0
____
ns
tSWRD
SEM Flag Write to Read Time
5
____
5
____
ns
tSPS
SEM Flag Contention Window
5
____
5
____
ns
NOTES:
5683 tbl 12
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access SRAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the entire
tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
6.1422
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