IDT72V845 Ver la hoja de datos (PDF) - Integrated Device Technology

Número de pieza

componentes Descripción

Lista de partido

IDT72V845

3.3 VOLT CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18

Integrated Device Technology 

IDT72V805/72V815/72V825/72V835/72V845

3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18

WCLK

WEN

tCLKH

tCLKL

tENS

tENH

PAE

RCLK

REN

n words in FIFO(2),

n + 1words in FIFO(3)

tSKEW2 (4)

tPAES

n + 1 words in FIFO(2),

n + 2 words in FIFO(3)

tENS

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tPAES

tENH

n Words in FIFO(2),

n + 1 words in FIFO(3)

4295 drw 22

NOTES:

1. n = PAE offset.

2. For IDT Standard Mode.

3. For FWFT Mode.

4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge

of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.

5. PAE is asserted and updated on the rising edge of RCLK only.

6. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.

Figure 22. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)

WCLK

WEN

tCLKH

tCLKL

tENS

tENH

PAF

RCLK

REN

D-(m+1) Words in FIFO

tPAFS

D - m Words in FIFO

tENS

tSKEW2(3)

tENH

tPAFS

D -(m+1) Words

in FIFO

4295 drw 23

NOTES:

1. m = PAF offset.

2. D = maximum FIFO Depth.

In IDT Standard Mode: D = 256 for the IDT72V805, 512 for the IDT72V815, 1,024 for the IDT72V825, 2,048 for the IDT72V835 and 4,096 for the IDT72V845. In FWFT Mode:

D = 257 for the IDT72V805, 513 for the IDT72V815, 1,025 for the IDT72V825, 2,049 for the IDT72V835 and 4,097 for the IDT72V845.

3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK and

the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed an extra WCLK cycle.

4. PAF is asserted and updated on the rising edge of WCLK only.

5. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.

Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)

20

Share Link: