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LAN91C110 Datasheet PDF : 56 Pages
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Table Of Contents
FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications
Datasheet
Chapter 1 General Description............................................................................................................................5
Chapter 2 Pin Configuration ...............................................................................................................................6
Chapter 3 Description of Pin Functions..............................................................................................................7
Chapter 4 Functional Description .....................................................................................................................11
4.1 Description of Blocks......................................................................................................................... 11
4.1.1 Clock Generator Block................................................................................................................ 11
4.2 CSMA/CD Block ................................................................................................................................ 11
4.2.1 DMA Block .................................................................................................................................. 11
4.2.2 Arbiter Block................................................................................................................................ 11
4.2.3 MMU Block.................................................................................................................................. 12
4.2.4 BIU Block .................................................................................................................................... 12
4.2.5 MAC-PHY Interface Block .......................................................................................................... 12
4.2.6 MII Management Interface Block ................................................................................................ 13
Chapter 5 Data Structures and Registers .........................................................................................................15
5.1 Packet Format in Buffer Memory ...................................................................................................... 15
5.2 Typical Flow of Events for Transmit (Auto Release = 0)................................................................... 37
5.3 Typical Flow of Events for Transmit (Auto Release = 1)................................................................... 38
5.4 Typical Flow of Events for Receive ................................................................................................... 40
5.5 Memory Partitioning .......................................................................................................................... 46
5.6 Interrupt Generation .......................................................................................................................... 46
Chapter 6 Operational Description...................................................................................................................49
6.1 Maximum Guaranteed Ratings* ........................................................................................................ 49
6.2 DC Electrical Characteristics............................................................................................................. 49
Chapter 7 Timing Diagrams ..............................................................................................................................51
Chapter 8 Package Outline ................................................................................................................................56
List of Figures
Figure 2.1 – Pin Configuration ...................................................................................................................... 6
Figure 3.1 - LAN91C110 Block Diagram..................................................................................................... 10
Figure 3.2 - LAN91C110 System Diagram ................................................................................................. 10
Figure 4.1 - LAN91C110 Internal Block Diagram with Data Path ............................................................... 14
Figure 5.1 – Data Packet Format................................................................................................................ 15
Figure 5.2 – Interrupt Structure................................................................................................................... 33
Figure 5.3 – Interrupt Service Routine ........................................................................................................ 41
Figure 5.4 - RX INTR .................................................................................................................................. 42
Figure 5.5 - TX INTR................................................................................................................................... 43
Figure 5.6 - TXEMPTY INTR (Assumes auto release option selected)...................................................... 44
Figure 5.7 - Drive Send and Allocate Routines........................................................................................... 45
Figure 5.8 – Interrupt Generation for Transmit, Receive, MMU.................................................................. 48
Figure 7.1 - Asynchronous Cycle - nADS=0 ............................................................................................... 51
Figure 7.2 - Asynchronous Cycle - USING nADS....................................................................................... 51
Figure 7.3 – Address Latching for All Modes .............................................................................................. 52
SMSC LAN91C110 Rev. B
Page 3
DATASHEET
Revision 1.0 (11-04-08)
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