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LAN91C110

FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications

SMSC -> Microchip 

FEAST Fast Ethernet Controller for PCMCIA and Generic 16-Bit Applications

Datasheet

Chapter 3 Description of Pin Functions

144 TQFP

PIN NO.

115-112,

110-100

138

118, 117

NAME

Address

Address

Enable

SYMBOL

A[15:1]

AEN

nBE[1:0]

89, 91-95, Data Bus

97-98, 119,

121-123,

125-128

135 Reset

D[15:0]

RESET

129 Asynchro- ARDY

nous

Ready

120 Local

nLDEV

Device

88

nAddress nADS

Strobe

131 Interrupt INTR0

132 nRead nRD

Strobe

134 nWrite nWR

Strobe

BUFFER

TYPE

I

I

I

I/O8

IS

OD16

O16

IS

O4

IS

DESCRIPTION

Input. Used by LAN91C110 for internal register

selection.

Input. Used as an address qualifier. Address

decoding is only enabled when AEN is low.

Input. Used during LAN91C110 register accesses

to determine the width of the access and the

register(s) being accessed.

Bidirectional. 16-bit data bus used to access the

LAN91C110’s internal registers. Data bus has

weak internal pullups. Supports direct connection

to the system bus without external buffering.

Input. This input is not considered active unless it

is active for at least 100ns to filter narrow glitches.

Open drain output. ARDY may be used when

interfacing asynchronous buses to extend

accesses. Its rising (access completion) edge is

controlled by the XTAL1 clock and, therefore,

asynchronous to the host CPU or bus clock.

Note: Asserted for 100 to 150ns for the

appropriate NO WAIT bit state in the Configuration

register. See the NO WAIT bit description for

complete information.

Output. Local Device. This active low output is

asserted when AEN is low and A4-A15 decode to

the LAN91C110 address programmed into the

high byte of the Base Address Register. nLDEV*

is a combinatorial decode of unlatched address

and AEN signals.

Input. Address strobe. For systems that require

address latching. The rising edge of nADS

indicates the latching moment of A[1:15] and AEN.

All LAN91C110 internal functions of A[1:15] and

AEN are latched.

Output. The interrupt output is enabled by

selecting the appropriate routing bits (INT SEL 1-

0) in the Configuration Register.

Input. Used in asynchronous bus interfaces.

IS

Input. Used in asynchronous bus interfaces.

SMSC LAN91C110 Rev. B

Page 7

DATASHEET

Revision 1.0 (11-04-08)

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