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MC145540

ADPCM Codec

Motorola => Freescale 

2.2.2 Analog Interface and Signal Path

2.2.2.1 TRANSMIT ANALOG

The transmit analog portion of this device includes a low-noise, three terminal operational amplifier

capable of driving a 2 kΩ load. This op amp has inputs of TI+ and TI – and its output is TG. This op amp is

intended to be configured in an inverting gain circuit. The analog signal may be applied directly to the TG

pin if this transmit op amp is independently powered down. Power down may be achieved by connecting

both the TI+ and TI – inputs to the VDD pin. The TG pin becomes high impedance when the transmit op

amp is powered down. The TG pin is internally connected to a time continuous three-pole anti-aliasing

pre-filter. This pre-filter incorporates a two-pole Butterworth active low-pass filter, followed by a single

passive pole. This pre-filter is followed by a single-ended to differential converter that is clocked at

512 kHz. All subsequent analog processing utilizes fully differential circuitry. The output of the differen-

tial converter is followed by the transmit trim gain stage. This stage is intended to compensate for gain

tolerances of external components such as microphones. The amount of gain control is 0 to 7 dB in 1 dB

steps. This stage accommodates only positive gain because the maximum signal levels of the output of

the input op amp are the same as the transmit filter and ADC, which should nominally be next to the clip

levels of this device’s circuitry. Any requirement for attenuation of the output of the input op amp would

mean that it is being overdriven. The gain is programmed via the SCP port in BR1 (b2:b0). The next

section is a fully-differential, 5-pole switched-capacitor low-pass filter with a 3.4 kHz frequency cutoff.

After this filter is a 3-pole switched-capacitor high-pass filter having a cutoff frequency of about 200 Hz.

This high-pass stage has a transmission zero at dc that eliminates any dc coming from the analog input

or from accumulated op amp offsets in the preceding filter stages. (This high-pass filter may be removed

from the signal path under control of the SCP port BR8 (b4).) The last stage of the high-pass filter is an

autozeroed sample and hold amplifier.

One bandgap voltage reference generator and digital-to-analog converter (DAC) are shared by the

transmit and receive sections. The autozeroed, switched-capacitor bandgap reference generates pre-

cise positive and negative reference voltages that are virtually independent of temperature and power

supply voltage. A binary-weighted capacitor array (CDAC) forms the chords of the companding struc-

ture, while a resistor string (RDAC) implements the linear steps within each chord. The encode process

uses the DAC, the voltage reference, and a frame-by-frame autozeroed comparator to implement a

successive-approximation analog-to-digital conversion (ADC) algorithm. All of the analog circuitry in-

volved in the data conversion (the voltage reference, RDAC, CDAC, and comparator) are implemented

with a differential architecture.

The nonlinear companded Mu-Law transfer curve of the ADC may be changed to 8-bit linear by BR8

(b5).

The input to the ADC is normally connected to the output of the transmit filter section, but may be

switched to measure the voltage at the VEXT pin for battery voltage monitoring. This is selected by the

I/O Mode in BR0 (b4:b3). In this mode, the ADC is programmed to output a linear 8-bit PCM word for the

voltage at VEXT which is intended to be read in BR9 (b7:b0). The data format for the ADC output is a

Don’t Care for the sign bit and seven magnitude bits. The scaling for the ADC is for 6.3 V at VEXT equals

full scale (BIN X111 1111). The ADPCM algorithm does not support dc signals.

2.2.2.2

TRANSMIT DIGITAL

The Digital Signal Processor (DSP) section of this device is a custom designed, interrupt driven, micro-

coded machine optimized for implementing the ADPCM algorithms. In the full duplex speech mode, the

DSP services one encode interrupt and one decode interrupt per frame (125 µs). The encode algorithm

(i.e., 16 kbps, 24 kbps, or 32 kbps ADPCM, or 64 kbps PCM) is determined by the length of the transmit

output enable at the FST pin. The length of the FST enable measured in transmit data clock (BCLKT)

cycles tells the device which encoding rate to use. This enable length information is used by the encoder

each frame. The transmit ADPCM word corresponding to this request will be computed during the next

frame and will be available a total of two frames after being requested. This transmit enable length

information can be delayed by the device an additional four frames corresponding to a total of six

frames. These six frames of delay allow the device to be clocked with the same clocks for both transmit

(encode) and receive (decode), and to be frame aligned for applications that require every sixth frame

signaling. It is important to note that the enable length information is delayed and not the actual ADPCM

MOTOROLA

MC145540

2-5

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