MC145540 Ver la hoja de datos (PDF) - Motorola => Freescale
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MC145540 Datasheet PDF : 116 Pages
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cycles per FST rising edge. If FST has jitter, the jitter must be measured in SPC clock cycles which will
be subtracted from 10, and the frequency tolerance for SPC should be tightened accordingly. (The SPC
clock may be optionally specified for higher frequencies. Contact the factory for more information.)
The analog sequencing function of the SPC clock may be eliminated by reprogramming the device to
use the BCLKR pin as the direct input for the required 256 kHz analog sequencing clock. The 256 kHz
clock applied at BCLKR must be an integer 32 times the FST 8 kHz clock and be approximately rising
edge aligned with the FST rising edge. This mode requires that the transmit and receive ADPCM trans-
fers be controlled by the BCLKT pin. This is reprogrammed via the SCP port in BR0 (b7).
2.2.7 Digital I/O
The MC145540 is programmable for Mu-Law or A-Law. The timing for the PCM data transfer is inde-
pendent of the companding scheme selected. Table 2-1 shows the 8-bit data word format for positive
and negative zero and full scale for both 64 kbps companding schemes. Refer to Section 2.4.3, Figures
2-3 through 2-7, for a summary and comparison of the five PCM data interface modes of this device.
2.2.7.1
LONG FRAME SYNC
Long Frame Sync is the industry name for one type of clocking format which controls the transfer of the
ADPCM or PCM data words. Refer to Section 2.4.3, Figures 2-3 through 2-6. The “Frame Sync” or
“Enable” is used for two specific synchronizing functions. The first is to synchronize the PCM data word
transfer, and the second is to control the internal analog-to-digital and digital-to-analog conversions.
The term “Sync” refers to the function of synchronizing the PCM data word onto or off of the multiplexed
serial PCM data bus, also known as a PCM highway. The term “Long” comes from the duration of the
frame sync measured in PCM data clock cycles. Long Frame Sync timing occurs when the frame sync is
used directly as the PCM data output driver enable. This results in the PCM output going low impedance
with the rising edge of the transmit frame sync, and remaining low impedance for the duration of the
transmit frame sync.
Level
+ Full Scale
+ Zero
– Zero
– Full Scale
Table 2-1. PCM Full Scale and Zero Words
Sign Bit
1
1
0
0
Mu-Law
Chord Bits
000
111
111
000
Step Bits
0000
1111
1111
0000
Sign Bit
1
1
0
0
A-Law
Chord Bits
010
101
101
010
Step Bits
1010
0101
0101
1010
Phase
π/8
3π/8
5π/8
7π/8
9π/8
11π/8
13π/8
15π/8
Table 2-2. PCM Codes for Digital mW
Sign Bit
0
0
0
0
1
1
1
1
Mu-Law
Chord Bits
001
000
000
001
001
000
000
001
Step Bits
1110
1011
1011
1110
1110
1011
1011
1110
Sign Bit
0
0
0
0
1
1
1
1
A-Law
Chord Bits
011
010
010
011
011
010
010
011
Step Bits
0100
0001
0001
0100
0100
0001
0001
0100
2-8
MC145540
MOTOROLA
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