MT9046(2003) Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc

Número de pieza

componentes Descripción

Lista de partido

MT9046
(Rev.:2003)

T1/E1 System Synchronizer with Holdover

Zarlink Semiconductor Inc 

MT9046

Data Sheet

(PRI or SEC). The input reference signal may have a nominal frequency of 8kHz, 1.544MHz, 2.048MHz or

19.44MHz.

From a reset condition, the MT9046 will take up to 30 seconds (see AC Electrical Characteristics) of input

reference signal to output signals which are synchronized (phase locked) to the reference input.

The selection of input references is control dependent as shown in state Table 4. The reference frequencies are

selected by the frequency control pins FS2 and FS1 as shown in Table 1.

Fast Lock Mode

Fast Lock Mode is a submode of Normal Mode, it is used to allow the MT9046 to lock to a reference more

quickly than Normal Mode will allow. Typically, the PLL will lock to the incoming reference within 500ms if the

FLOCK pin is set high.

Holdover Mode

Holdover Mode is typically used for short durations (e.g., 2 seconds) while network synchronization is

temporarily disrupted.

In Holdover Mode, the MT9046 provides timing and synchronization signals, which are not locked to an external

reference signal, but are based on storage techniques. The storage value is determined while the device is in

Normal Mode and locked to an external reference signal

When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the

MT9046 output reference frequency is stored alternately in two memory locations every 30ms. When the device

is switched into Holdover Mode, the value in memory from between 30ms and 60ms is used to set the output

frequency of the device.

The frequency accuracy of Holdover Mode is ±0.2ppm, which translates to a worst case 1 frame (125us) slip in

10 minutes.

Two factors affect the accuracy of Holdover Mode. One is drift on the Master Clock while in Holdover Mode, drift

on the Master Clock directly affects the Holdover Mode accuracy. Note that the absolute Master Clock (OSCi)

accuracy does not affect Holdover accuracy, only the change in OSCi accuracy while in Holdover. For

example, a ±32ppm master clock may have a temperature coefficient of ±0.1ppm per degree C. So a ±10

degree change in temperature, while the MT9046 is in Holdover Mode may result in an additional offset (over

the ±0.2ppm) in frequency accuracy of ±1ppm.

The other factor affecting accuracy is large jitter on the reference input prior (30ms to 60ms) to the mode switch.

For instance, jitter of 7.5UI at 700Hz may reduce the Holdover Mode accuracy from ±0.2ppm to ±0.25ppm.

Freerun Mode

Freerun Mode is typically used when a master clock source is required, or immediately following system power-

up before network synchronization is achieved.

In Freerun Mode, the MT9046 provides timing and synchronization signals which are based on the master clock

frequency (OSCi) only, and are not synchronized to the reference signals (PRI and SEC).

The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a ±32ppm output

clock is required, the master clock must also be ±32ppm. See Applications - Crystal and Clock Oscillator

sections.

10

Zarlink Semiconductor Inc.

Share Link: