MT9046(2003) Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc

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MT9046
(Rev.:2003)

T1/E1 System Synchronizer with Holdover

Zarlink Semiconductor Inc 

Features

• Supports AT&T TR62411 and Bellcore GR-1244-

CORE, Stratum 4 Enhanced and Stratum 4 timing

for DS1 interfaces

• Supports ETSI ETS 300 011, TBR 4, TBR 12 and

TBR 13 timing for E1 interfaces

• Selectable 19.44 MHz, 1.544MHz, 2.048MHz or

8kHz input reference signals

• Provides C1.5, C2, C4, C6, C8, C16, and C19

(STS-3/OC3 clock divided by 8) output clock

signals

• Provides 5 styles of 8 KHz framing pulses

• Holdover frequency accuracy of 0.2 PPM

• Holdover indication

• Attenuates wander from 1.9Hz

• Fast lock mode

• Provides Time Interval Error (TIE) correction

• Accepts reference inputs from two independent

sources

• JTAG Boundary Scan

Applications

• Synchronization and timing control for Customer

Premises Equipment (CPE)

• ST-BUS clock and frame pulse sources

OSCi

OSCo

TCLR

MT9046

T1/E1 System Synchronizer

with Holdover

Data Sheet

January 2003

Ordering Information

MT9046AN

48 pin SSOP

-40°C to +85°C

Description

The MT9046 T1/E1 System Synchronizer contains a

digital phase-locked loop (DPLL), which provides

timing and synchronization signals for multitrunk T1

and E1 primary rate transmission links. The device

has reference switching and frequency holdover

capabilities to help maintain connectivity during

temporary synchronization interruptions.

The MT9046 generates ST-BUS clock and framing

signals that are phase locked to either a 19.44 MHz,

2.048MHz, 1.544MHz, or 8kHz input reference.

The MT9046 is compliant with AT&T TR62411 and

Bellcore GR-1244-CORE Stratum 4 Enhanced, and

Stratum 4 and ETSI ETS 300 011 interfaces. It will

meet the jitter tolerance, jitter transfer, intrinsic jitter,

LOCK VDD VSS

TCK

TDI

TMS

TRST

TDO

PRI

SEC

RSEL

Master Clock

IEEE

1149.1a

TIE

Corrector

Circuit

Virtual

Reference

DPLL

Reference

Select

MUX

Selected

Reference

TIE

Corrector

Enable

Reference

Select

State

Select

State

Select

Input

Impairment

Monitor

Control State Machine

Feedback

Output

Interface

Circuit

Frequency

Select

MUX

C19o

C1.5o

C2o

C4o

C6o

C8o

C16o

F0o

F8o

F16o

RSP

TSP

MS1 MS2 RST HOLDOVER PCCi FLOCK

FS1

FS2

Figure 1 - Functional Block Diagram

1

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