MT9046(2003) Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc

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MT9046
(Rev.:2003)

T1/E1 System Synchronizer with Holdover

Zarlink Semiconductor Inc 

Data Sheet

MT9046

Frequency Select MUX Circuit

The MT9046 operates with one of four possible input reference frequencies (8kHz, 1.544MHz, 2.048MHz or

19.44MHz). The frequency select inputs (FS1 and FS2) determine which of the four frequencies may be used

at the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset

(RST) must be performed after every frequency select input change. See Table 1.

FS2

FS1

Input Frequency

0

0

19.44MHz

0

1

8kHz

1

0

1.544MHz

1

1

2.048MHz

Table 1 - Input Frequency Selection

Time Interval Error (TIE) Corrector Circuit

The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or

SEC) from causing a step change in phase at the input of the DPLL block of Figure 1.

During reference input rearrangement, such as during a switch from the primary reference (PRI) to the

secondary reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of

the DPLL would lead to unacceptable phase changes in the output signal.

TCLR

Resets Delay

Control

Circuit

Control Signal

Delay Value

PRI or SEC

from

Reference

Select Mux

Programmable

Delay Circuit

Compare

Circuit

Virtual

Reference

to DPLL

TIE Corrector

Enable

from

State Machine

Feedback

Signal from

Frequency

Select MUX

Figure 3 - TIE Corrector Circuit

As shown in Figure 3, the TIE Corrector Circuit receives one of the two reference (PRI or SEC) signals, passes

the signal through a programmable delay line, and uses this delayed signal as an internal virtual reference,

which is input to the DPLL. Therefore, the virtual reference is a delayed version of the selected reference.

During a switch from one reference to the other, the State Machine first changes the mode of the device

from Normal to Holdover. In Holdover Mode, the DPLL no longer uses the virtual reference signal, but

generates an accurate clock signal using storage techniques. The Compare Circuit then measures the phase

delay between the current phase (feedback signal) and the phase of the new reference signal. This delay value

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