MT9046(2003) Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc

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MT9046
(Rev.:2003)

T1/E1 System Synchronizer with Holdover

Zarlink Semiconductor Inc 

MT9046

Data Sheet

frequency accuracy, capture range, phase change slope frequency and MTIE requirements for these

specifications.

VSS

1

48 TMS

RST 2

47 TCK

TCLR 3

46 TRST

NC 4

45 TDI

SEC 5

44 TDO

PRI 6

43 NC

Vdd 7

42 IC

OSCo 8

41 FS1

OSCi 9

40 FS2

Vss 10

39 IC

F16o 11

F0o 12

SSOP

38

37

RSEL

MS1

RSP

TSP

13

14

36 MS2

35 Vdd

F8o 15

34 IC

C1.5o 16

33 IC

Vdd 17

32 NC

LOCK 18

31 Vss

C2o 19

30 PCCi

C4o 20

29 HOLDOVER

C19o 21

28 Vdd

FLOCK 22

27 C6o

Vss 23

26 C16o

IC 24

25 C8o

Figure 2 - Figure 2 - Pin Connections

Pin Description

Pin #

1,10,

23,31

2

3

4

5

6

7,17

28,35

Name

VSS

Ground. 0 Volts. (Vss pads).

Description

RST

TCLR

NC

SEC

PRI

VDD

Reset (Input). A logic low at this input resets the MT9046. To ensure proper operation, the

device must be reset after reference signal frequency changes and power-up. The RST pin

should be held low for a minimum of 300ns. While the RST pin is low, all frame pulses

except RST and TSP and all clock outputs except C6o, C16o and C19o are at logic high.

The RST, TSP, C6o and C16o are at logic low during reset. The C19o is free-running

during reset. Following a reset, the input reference source, output clocks and frame pulses

are phase aligned as shown in Figure 13.

TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE)

correction circuit resulting in a realignment of input phase with output phase as shown in

Figure 13. The TCLR pin should be held low for a minimum of 300ns. This pin is internally

pulled down to VSS.

No Connection. Leave open Circuit

Secondary Reference (Input). This is one of two (PRI & SEC) input reference sources

(falling edge) used for synchronization. One of four possible frequencies (8kHz, 1.544MHz,

2.048MHz or 19.44MHz) may be used. The selection of the input reference is based upon the

MS1, MS2, RSEL, and PCCi control inputs.This pin is internally pulled up to VDD.

Primary Reference (Input). See pin description for SEC. This pin is internally pulled up to

VDD.

Positive Supply Voltage. +3.3VDC nominal.

2

Zarlink Semiconductor Inc.

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