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NM95MS18

Plug & Play Front-end device for ISA-Bus Systems (Supports Windows®-NT, UNIX® and legacy systems)

Fairchild Semiconductor 

Internal EEPROM Memory of NM95MS18 (Continued)

PROGRAMMING INTERFACE

Programming EEPROM Register

Name

Status and Command Register

Register

0xF0

Address Register

Data Register

Data Register

STATUS Register

0xF1

0xF2

0xF3

0x05

Definition

Bit[1:0} OP Code bits

10 - Read operation

01 - Write operation

11 - Erase operation

Bit [2] - GA (Go Ahead bits)

If set to 1, the programming will continue

Bit [7:3] - Reserved, should be 0

Address register [A0 - A7]

Data Byte [MSB]

Data Byte [LSB]

Bit [0]: STATUS/BUSY bit during programming, ‘0’ is BUSY, ‘1’ is done

PROGRAMMING WHEN “WRITE-PROTEC-

TION” IS ENABLED

In this case, programming is enabled when N_PNP* pin is “0” and

the SW[0:4] inputs are “11111”. Programming procedure is same

as programming when Write-Protection is disabled with the ex-

ception of LFSR sequence. In this case 33-Byte Extended-LSFR

should be used instead of 32-Byte LFSR.

PROGRAMMING THROUGH MICROWIRE

INTERFACE (TEST MODE)

This method is suited when NM95MS18 is pre-programmed

before board assembly. This method involves using special TEST

mode of NM95MS18. Once the device is in TEST mode, the entire

internal memory can be programmed like a standard Micro-wire

EEPROM. The protocol to place the device in “test-mode” makes

use of the following three signals, viz. RESETDRV, IRQIN0 and

SW0. The timing diagram is shown below.

RESTDRV

IRQIN0

SW0

500 ns

100 ns

5V

5V

500 ns

12V

100 ns

100 ns

300 ns

Note: All timings shown here are minimum values.

100 ns

Start of standard

Micro-wire

access

DS500033-10

10

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