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PCA9561 Datasheet PDF : 26 Pages
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NXP Semiconductors
PCA9561
Quad 6-bit multiplexed I2C-bus EEPROM DIP switch
6. Functional description
Refer to Figure 1 “Block diagram of PCA9561”.
6.1 Device address
Following a START condition the bus master must output the address of the slave it is
accessing. The address of the PCA9561 is shown in Figure 3. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
The last bit of the slave address byte defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
Fig 3. Slave address
MSB
LSB
1 0 0 1 1 A1 A0 R/W
fixed
hardware
selectable
002aah287
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9561, which will be stored in the Control register. This register can be
written and read via the I2C-bus.
Fig 4. Control register
D7 D6 D5 D4 D3 D2 D1 D0
002aah288
6.2.1 Control register definition
Following the address and acknowledge bit with logic 0 in the read/write bit, the first byte
written is the command byte. If the command byte is reserved and therefore not valid, it
will not be acknowledged. Only valid command bytes will be acknowledged.
Table 4. Address register
D7 D6 D5 D4 D3 D2 D1 D0 Register name
0
0
0
0
0
0
0
0 EEPROM_0
0
0
0
0
0
0
0
1 EEPROM_1
0
0
0
0
0
0
1
0 EEPROM_2
0
0
0
0
0
0
1
1 EEPROM_3
1
1
1
1
1
1
1
1 MUX_IN
Type
read/write
read/write
read/write
read/write
read
Register function
EEPROM byte 0 register
EEPROM byte 1 register
EEPROM byte 2 register
EEPROM byte 3 register
MUX_IN values register
PCA9561
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 November 2012
© NXP B.V. 2012. All rights reserved.
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