PEB20954(1999) Ver la hoja de datos (PDF) - Infineon Technologies

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PEB20954
(Rev.:1999)

Smart Integrated Digital Echo Canceller

Infineon Technologies 

2.2

Pin Definitions and Functions

PEB 20954

PEF 20954

Pin Descriptions

Table 1

General Pins

Pin No. Symbol

Input (I)

Output (O)

Pull Up /

Pull Down

Function

114 PORES

I, PU

Power On Reset. A low on this pin forces all

registers and counters to predefined values

112 MODE1

113 MODE0

I, PU

I, PU

1

End delay < 1

For future use

1

64ms

0

112 MODE1

113 MODE0

I, PU

I, PU

0

End delay < 0

End delay <

1

128 ms Master 0

128 ms Slave

Mode

Mode

Table 2

Synchronization

Pin No. Symbol

111

CLK32SEL

126

CLK32

123 CTRL32

130 SCLKI

119 SCLKO

117 CLK4O

I/O, PU/PD Function

I, PU

Selects from which source SCLKO will be

derived:

’1’: SCLKO will be derived from CLK32 by

dividing by 4

’0’: SCLKO will be derived from CLK16 by

dividing by 2

I, PU

32.768 MHz Operating Clock for the SIDEC

O

Control voltage for the 32.768 MHz operating

Clock VCO, maskable for reduced power

consumption

I, PU

System clock input (8.192 MHz) for PCM- and

UCCI

O

8.192 MHz system clock output, source CLK32

or CLK16 is selectable via pin CLK32SEL,

maskable for reduced power consumption

O

4.096 MHz system clock output for subsequent

circuits, derived from SCLKI, maskable for

reduced power consumption

Preliminary Data Sheet

14

04.99

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