PEB20954(1999) Ver la hoja de datos (PDF) - Infineon Technologies

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PEB20954
(Rev.:1999)

Smart Integrated Digital Echo Canceller

Infineon Technologies 

Pin No. Symbol

92

SO

91

RO

88

SO128

87

RO128

PEB 20954

PEF 20954

Pin Descriptions

I/O, PU/PD Function

O

2.048 Mbit/s Send speech highway output.

Start of timeslot 0, bit 7 can be flexibly aligned

to the SYNCI/SYNCO pulse in 122 ns steps via

registers SOALIGN and PHALIGN[5:4]

O

2.048 Mbit/s Receive speech highway output.

This signal will has a fixed delay of one PCM

frame (125 µs) with respect to RI

I/O, PU

Auxiliary 2.048 Mbit/s Send speech highway

output in 128 ms mode. Input in master mode,

output in slave mode. The pins of master and

slave SIDEC in 128 ms mode should be

connected to enable a 32 channel system. The

signal from the slave is multiplexed in the

master with the internally generated signal and

output (clocked) with the system clock. Tristate

and meaningless in 64 ms mode

I/O, PU

Auxiliary 2.048 Mbit/s Receive speech

highway output in 128 ms mode. Input in

master mode, output in slave mode. The pins

of master and slave SIDEC in 128 ms mode

should be connected to enable a 32 channel

system. The signal from the slave is

multiplexed in the master with the internally

generated signal and output (clocked) with the

system clock. Tristate and meaningless in 64

ms mode

Preliminary Data Sheet

19

04.99

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