PEB20954(1999) Ver la hoja de datos (PDF) - Infineon Technologies

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PEB20954
(Rev.:1999)

Smart Integrated Digital Echo Canceller

Infineon Technologies 

PEB 20954

PEF 20954

Pin Descriptions

Table 4

Microcontroller Port Extension

Pin No. Symbol

27

UPIO0

28

UPIO1

29

UPIO2

30

UPIO3

I/O, PU/PD

I/O, PU

I/O, PU

I/O, PU

I/O, PU

Function

Pin that can be read and controlled by the on

board processor via register UPIO

Pin that can be read and controlled by the on

board processor via register UPIO

Pin that can be read and controlled by the on

board processor via register UPIO

Pin that can be read and controlled by the on

board processor via register UPIO

Table 5

Processor Watchdog Circuit

Pin No. Symbol

63

UPRES

62

UPRES

33

DISWD

34

UPRESI

I/O, PU/PD Function

O

µP-Reset. High pulse (125 µs) if the µP fails to

write predefined values to the registers WDG1

to WDG3 in this sequence within 2 s and

DISWD=’1’. Also active if PORES=’0’ or

UPRESI=’0’

O

Same as UPRES, but low active

I, PU

Disable of µP-Reset on active watchdog

condition if set to low

I, PU

Produces a reset signal at UPRES, UPRES if

set to low

Table 6

Speech Highways

Pin No. Symbol

84

SI

83

RI

I/O, PU/PD

I, PD

I, PD

Function

2.048 Mbit/s Send speech highway input. Start

of timeslot 0, bit 7 can be flexibly aligned to the

SYNCI/SYNCO pulse in 122 ns steps via

registers SIALIGN and PHALIGN[3:2]

2.048 Mbit/s Receive speech highway input.

Start of timeslot 0, bit 7 can be flexibly aligned

to the SYNCI/SYNCO pulse in 122 ns steps via

registers RIALIGN and PHALIGN[1:0]

Preliminary Data Sheet

18

04.99

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