PEB20954(1999) Ver la hoja de datos (PDF) - Infineon Technologies

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PEB20954
(Rev.:1999)

Smart Integrated Digital Echo Canceller

Infineon Technologies 

PEB 20954

PEF 20954

Pin Descriptions

Table 3

Microprocessor Interface

Pin No. Symbol

78

IM0

77

IM1

71

CS0

70

CS1

46-43

40-38

58-55

52-49

67

A0..A6

AD0..AD7

ALE

69

RD/DS

68

WR/RW

64

INT

61

RDY

I/O, PU/PD Function

I, PU

Interface Mode SIEMENS/Intel = low,

Motorola = high

I, PU

Interface Mode MUXED = low, DEMUXED =

high

I, PU

Chip Select. A low signal selects the SIDEC

(internally "anded" with CS1).

I, PU

Chip Select. A low signal selects the SIDEC

(internally "anded" with CS0).

I, PU

Address Bus. Only used in demuxed mode,

can be left open in muxed mode.

I/O, -

Multiplexed Address/Data Bus in multiplexed

mode, Data Bus in demultiplexed mode

I, PU

Address Latch Enable in multiplexed mode.

Address on AD bus is internally latched with

the falling edge of ALE.This signal is also used

for the internal clock supervision.

In Demuxed mode there must be provided an

external independent clock signal (i.e.

processor clock) in order to enable proper

clock supervision.

I, PU

SIEMENS/Intel mode. A low indicates a read

operation.

Motorola mode. Data Strobe, active low to

control read/write

I, PU

SIEMENS/Intel mode. A low indicates a write

operation.

Motorola mode. High = read cycle,

low = write cycle

O, (od)

Interrupt request from the SIDEC, active low

O, (od)

Ready signal for µC devices that support this

feature. For read cycles the signal is asserted

after the data on the AD bus is valid. For writing

cycles the signal is asserted when a write

access is ready to be concluded.

Preliminary Data Sheet

17

04.99

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