RTL8101 Ver la hoja de datos (PDF) - Unspecified
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RTL8101 Datasheet PDF : 68 Pages
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RTL8101L
ANE = 0 &
-
half-duplex mode
invalid
NWAY FLY mode: NWAY with flow control capability
NWAY mode only: NWAY without flow control capability
6
R/W
RXFCE
RX Flow control Enable: The flow control is enabled in full-duplex
mode only. The default value comes from 93C46.
5
-
-
Reserved
4
R
Aux_Status
Aux. Power present Status:
1: The Aux. Power is present.
0: The Aux. Power is absent.
The value of this bit is fixed after each PCI reset.
3
R
SPEED_10
Speed: Set, when current media is 10 Mbps mode. Reset, when current
media is 100 Mbps mode.
2
R
LINKB
Inverse of Link status. 0 = Link OK. 1 = Link Fail.
1
R
TXPF
Transmit Pause Flag: Set, when RTL8101L sends pause packet. Reset,
when RTL8101L sends a timer done packet.
0
R
RXPF
Receive Pause Flag: Set, when RTL8101L is in backoff state because a
pause packet was received. Reset, when pause state is clear.
5.13 CONFIG 3: Configuration Register3
(Offset 0059h, R/W)
Bit
R/W
Symbol
7
R
GNTSel
6
R/W
PARM_En
5
R/W
Magic
Description
Gnt Select: Select the Frame’s asserted time after the Grant signal has
been asserted. The Frame and Grant are the PCI signals.
1: delay one clock from GNT assertion.
0: No delay
Parameter Enable: (Used in 100Mbps mode only)
This set to 0 and the 9346CR register EEM1=EEM0=1 will enable the
PHY1_PARM, PHY2_PARM, and TW_PARM registers to be written via software.
This set to 1 will allow parameters to be auto-loaded from the 93C46
and disable writing to the PHY1_PARM, PHY2_PARM and
TW_PARM registers via software.
The PHY1_PARM and PHY2_PARM can be auto-loaded from the
EEPROM in this mode. The parameter auto-load process is executed
every time the Link is OK in 100Mbps mode.
Magic Packet: This bit is valid when the PWEn bit of the CONFIG1
register is set. The RTL8101L will assert the PMEB signal to wakeup the
operating system when the Magic Packet is received.
Once the RTL8101L has been enabled for Magic Packet wakeup and
has been put into adequate state, it scans all incoming packets addressed
to the node for a specific data sequence, which indicates to the controller
that this is a Magic Packet frame. A Magic Packet frame must also meet
the basic requirements of:
Destination address + Source address + data + CRC
The destination address may be the node ID of the receiving station or a
multicast address, which includes the broadcast address.
The specific sequence consists of 16 duplications of 6 byte ID registers,
with no breaks or interrupts. This sequence can be located anywhere
within the packet, but must be preceded by a synchronization stream, 6
bytes of FFh. The device will also accept a multicast address, as long as
the 16 duplications of the IEEE address match the address of the ID
registers.
2003-05-28
22
Rev.1.3
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