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SAA4952WP

Memory controller

Philips Electronics 

Philips Semiconductors

Memory controller

Objective specification

SAA4952WP

Table 10 Mode1 register description

REGISTER BIT

MODE1

0

1

2

3

4

5

6

7

NAME

DR

STPWM1

STPWM2

SD0

GSC

SD1

EXTLLA

VFS

REMARKS

display raster

stop writing to memory 1; still picture mode; STROBE signal can override still

picture mode

stop writing to memory 2; still picture mode

select mode of display signal at pin 17; bit 0

golden SCART mode

GSC = 0: normal operation

GSC = 1: golden SCART mode

select mode of display signal at pin 17; bit 1; see Table 11

external acquisition clock

EXTLLA = 0: normal operation

EXTLLA = 1: LLA and horizontal reference pulse BLNA (horizontal reset)

from external digital source

vertical frequency select

VFS = 0: 100/120 Hz

VFS = 1: 50/60 Hz

Table 11 Signal mode at pin 17

SD1

SD0

MODE

0

0

horizontal signal HD at the output

0

1

vertical signal VD at the output

1

0

composite signal CD (derived from HD and VD by AND connection) at the output

1

1

composite signal CD at the output

Table 12 Display modes

CONTROL BITS

VFS(1)

SSC(2)

DR(3)

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

DISPLAY MODE (NUMBER OF LINES VALID FOR STANDARD PAL)

100 Hz (312.5 lines) ABAB raster

100 Hz (313, 312.5, 312 and 312.5 lines) AABB raster

not allowed

not allowed

50 Hz (625 lines) 1 : 1; non-interlaced

50 Hz (1250 lines) 2 : 1; interlaced

50 Hz (312.5 lines) 2 : 1

not allowed

Notes

1. VFS: Vertical Frequency Select; register MODE1; bit 7.

2. SSC: Select Single Clock SAA4952WP input pin 41.

3. DR: Display Raster; register MODE1; bit 0.

1997 Jun 10

13

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