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SAA4952WP

Memory controller

Philips Electronics 

Philips Semiconductors

Memory controller

Objective specification

SAA4952WP

Table 18 Delay table (see Fig.9)

Worst case conditions: VDD = 4.5 V and Tamb = 85 °C. Typical case conditions: VDD = 5 V and Tamb = 25 °C.

CLK

OUTPUT

LOAD

(pF)

th(min)

(ns)

th(typ)

(ns)

tpd(max)

(ns)

tpd(typ)

(ns)

LLA

SWC1

15

2

LLA

SWC05

15

4

LLD

SRC

45

3

LLDFL(1)

SRC

45

3

LLA

WE1

15

7

LLD

WE2

10

7

LLD

RE1

10

8

LLD

RE2

10

7

LLDFL

HDFL

25

7

LLD

BLND

25

8

LLD

HVCD

25

8

LLA

CLV

25

7

LLDFL

VDFL

25

7

3

11

8

5

13

10

4

10

8

4

10

8

8

18

13

8

18

13

9

18

13

7

18

13

7

12

10

9

19

13

8

20

15

8

12

10

7

12

9

Note

1. Source for SRC depends on the setting of register MODE0 and the level on the SDP pin.

handbook, full pagewidth

HRA

CLV

HWE1

HVACQS

CLVf

HWE1r

HVACQS1

CLVr

HWE1f

HVACQS2

1997 Jun 10

Fig.4 Horizontal acquisition timing.

19

MHA725

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