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SAA4952WP

Memory controller

Philips Electronics 

Philips Semiconductors

Memory controller

Objective specification

SAA4952WP

HVCD

The memory controller supplies a display related output

which can generate, depending on the microcontroller

initialization, three different signals. The desired mode is

activated via microcontroller register MODE1 (control bits

SD0 and SD1).

Table 14 Mode setting of SAA4952WP output HVCD

SD1 SD0

MODE OF OUTPUT PIN 17

0 0 horizontal output signal HD; programmable

via HDSTA and HDSTO

0 1 vertical output signal VD; programmable via

VDSTA and VDSTO

1 X composite output signal HVCD; logical

AND connection of HD and VD

IE2

This output signal is used as data input enable for

memory 2. A logic HIGH level on this output pin enables

the data information to be written to field memory 2.

RE1

The output RE1 is the read enable signal for field

memory 1. A HIGH level enables the picture data to be

read from the memory. RE1 is a composite signal and

includes the horizontal read enable timing (HRE) and the

vertical read enable timing (VRE). It is possible to delay the

horizontal timing of RE1 by up to three display clock

pulses. The horizontal timing of RE1 and RE2 is equal.

RE2

The output RE2 is the read enable signal for field

memory 2. A HIGH level enables the picture data to be

read from memory. RE2 is a composite signal and includes

the horizontal read enable timing (HRE) and the vertical

read enable timing (VRE2). The horizontal timing of RE2

can be delayed by up to three display clock pulses.

The new memory controller supplies two completely

independent VRE signals, VRE1 and VRE2. VRE1 is not

generated as an adjustable delay of VRE2 as in the

SAA4951WP.

Table 15 Programming range of horizontal display signals (BLND, HRE, HWE2, HD and HVSP1 to HVSP4); see Fig.6

Nr (programmed start (rise) value of corresponding signal) not equal Nf (programmed stop (fall) value of corresponding

signal).

ACQUISITION FREQUENCY

(MHz)

27

32

36

TIMING EQUATIONS

HDSPr = (2Nr + 2)LLD

HDSPf = (2Nf + 2)LLD

HVSPn(1) = (4N(2) + 2)LLD

HDSPr = (2Nr + 2)LLD

HDSPf = (2Nf + 2)LLD

HVSPn(1) = (4N(2) + 2)LLD

HDSPr = (4Nr + 4)LLD

HDSPf = (4Nf + 4)LLD

HVSPn(1) = (8N(2) + 4)LLD

PROGRAMMING RANGE

0 ≤ Nr < 431

0 ≤ Nf < 431

0 ≤ N < 215

0 ≤ Nr < 511

0 ≤ Nf < 511

0 ≤ N < 255

0 ≤ Nr < 287

0 ≤ Nf < 287

0 ≤ N < 145

Notes

1. HVSPn = HVSP1 to HVSP4.

2. N: programmed value of HVSP pulse.

LLD equals LLDFL for 27 MHz display in the three-clock system.

LLD input is not used in the two-clock mode (internally switched to LLDFL input).

The programmed values include the MSB settings contained in HDMSB.

1997 Jun 10

17

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