SAA6750 Ver la hoja de datos (PDF) - Philips Electronics

Número de pieza

componentes Descripción

Lista de partido

SAA6750

Encoder for MPEG2 image recording (EMPIRE)

Philips Electronics 

Philips Semiconductors

Encoder for MPEG2 image recording

(EMPIRE)

Product specification

SAA6750H

1 FEATURES

• Digital YUV input according to “ITU-T 601” and

“ITU-T 656”

• NTSC and PAL (720 pixels × 480 lines at 60 Hz and

720 pixels × 576 lines at 50 Hz)

• Integrated colour conversion 4 : 2 : 2 to 4 : 2 : 0

• Integrated format conversion to SIF format (optional)

• Real time MPEG2 Simple Profile at Main Level

(SP@ML) encoding

• IP frame or I frame only encoding supported

• Programmable Group Of Pictures (GOP) size

• Integrated motion estimation, half pixel accuracy

• Motion compensated noise reduction

• Elementary stream data output compliant to MPEG2

standard (“ISO 13818-2”)

• Bitstream output compatible to 16-bit parallel interface

with Motorola (68xxx like) protocol style

• No external host processor required

• 4 × 4 Mbit external DRAM required

• I2C-bus controlled

• Single external video clock 27 MHz

• Power supply voltage 3.3 V

• Digital inputs 5 V tolerant

• Boundary Scan Test (BST) supported.

2 GENERAL DESCRIPTION

2.1 General

The SAA6750H is a new approach towards a stand-alone

MPEG2 video encoder IC. It combines high quality

SP@ML compliant real time encoding with

cost-effectiveness, allowing for the first time the use of an

MPEG2 encoder IC in applications and markets with a

high cost pressure. This has been achieved by means of a

number of innovations in architecture and algorithms

developed by the Philips Research Laboratories, e.g.:

• The unique motion estimation algorithm supports highly

efficient encoding by using only I frame and IP frame

mode. B frames need not be used. This leads to a

significantly smaller internal circuitry and also reduces

DRAM memory requirements from at least 4 to 2 Mbyte.

In addition, the absence of B frames simplifies editing of

the compressed data stream.

• The patented, motion-compensated temporal noise

filtering which was developed by Philips for professional

equipment reduces noise in the input video before

compression is performed. This technique gives visible

improvements in picture quality, especially in the field of

home recordings with noisy signal sources where this

has proved to be of significant benefit.

Internally the SAA6750H uses a hardware solution for data

compression and a specially developed high performance

processor for control purposes.

2.2 Function

The SAA6750H is a stand-alone single chip video encoder

performing real time MPEG2 compression of digital video

data.

The video data input of the SAA6750H accepts a digital

YUV video data stream in ITU-T 601 format. PAL standard

at 50 Hz and 720 pixels by 576 lines, as well as NTSC at

60 Hz and 720 pixels by 480 lines, are covered. The video

synchronization may either follow ITU-T 656

recommendation or can also be supplied by external

signals. The external reference clock of 27 MHz to

pin VCLK has to be synchronized to the video data. The

product family SAA7111 of Philips Semiconductors

provides a suitable video data stream and reference clock.

Other sources are also supported by the flexible I2C-bus

controlled data input interface of the SAA6750H.

See Section 7.3 for detailed information.

An internal 4 : 2 : 2 to 4 : 2 : 0 colour format conversion is

performed. Optionally, a ITU-T 601 to SIF format

conversion may be activated by the I2C-bus control

settings.

The real time data encoding part of the SAA6750H

combines high-compression rates with high quality picture

performance. This is achieved by the integration of Philips

unique motion estimation algorithm and a patented

motion-compensated noise filtering. The compression

algorithm uses I or IP mode encoding. Normally it selects

automatically the suitable mode but may also be forced to

I mode operating only by the I2C-bus control settings.

2000 May 03

3

Share Link: