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SAA6750

Encoder for MPEG2 image recording (EMPIRE)

Philips Electronics 

Philips Semiconductors

Encoder for MPEG2 image recording

(EMPIRE)

Product specification

SAA6750H

In contrast to the encoding part which is designed in

dedicated hardware, control functions and data stream

handling tasks such as e.g. header generation and bit-rate

control are carried out by a dedicated control processor,

the so-called Application Specific Instruction-set

Processor (ASIP). The ASIP’s microcode is contained in

an internal RAM and is loaded via the I2C-bus before start

of operation.

The ASIP is able to communicate with the outside world

via the I2C-bus.

The SAA6750H generates an MPEG2 Elementary

Stream (ES) in accordance with the MPEG2 standard

(“ISO 13818-2”). The 16-bit data output interface supports

Motorola (68xxx like) protocol style.

Data processing and control functions are managed by

loosely coupled processes. FIFO memories are used to

connect these processes. In addition to these internal

storages the SAA6750H needs 4 × 4 Mbit of external

DRAM memory (tRAC = 60 ns). A block diagram is shown

in Fig.1.

Selectable I2C-bus addresses and a special reset mode

affecting the output pin behaviour allow the use of two

SAA6750H devices in one application.

2.3 Application fields

2.3.1 GENERAL

The SAA6750H can be applied within the following

application domains:

• Video editing (PC applications)

• Camera signal transmission

• Digital Versatile Disc (DVD) recording

• Video recording for surveillance

• Digital VCR.

All those systems have to compress video data in order to

manage the storage or transmission of digitized video

data. The SAA6750H can be handled for most of the

applications as a stand-alone device. That means at

start-up a microcode and a couple of the I2C-bus settings

are loaded and the SAA6750H is started. If needed,

settings such as GOP size or bit-rate are changed

on-the-fly via the I2C-bus.

2.3.2 VIDEO EDITING (PC APPLICATIONS)

For video editing the SAA6750H can be interfaced

gluelessly to a video input processor with ITU-T 656

compliant digital video output. In order to link the

SAA6750H to the PC, the use of the PCI bridge SAA7146

is recommended. By this bridge the MPEG2 video ES can

be transmitted via the PCI-bus to a HardDisc (HD).

Furthermore all the I2C-bus settings can be send from

the PC via the bridge to the I2C-bus components on the

encoder board. The SAA7146 supports Pulse Code

Modulation (PCM) audio capturing. Multiplexing with an

audio stream or audio encoding can be done by the CPU

of the PC. A block diagram is shown in Fig.18.

2.3.3 CAMERA SIGNAL TRANSMISSION

In this application the SAA6750H will be located inside a

camera to compress the received digital video data for

transmission.

2.3.4 VIDEO RECORDING FOR SURVEILLANCE

For surveillance systems VCRs with a huge amount of

storage capacity are required. A high picture resolution is

very important when there is action in the captured picture.

The SAA6750H can control the encoded bit-rate by motion

detection by its integrated motion estimation algorithm.

Doing so the bit-rate can vary from 0.5 to 10 Mbit/s.

VCRs with a storage space of 6 month are possible.

2.3.5 DIGITAL VCR

In stand-alone VCRs the SAA6750H works together with

an audio encoder and a multiplexer. The SAA6750H is

clocked by the video clock of the video input processor

(SAA7111 or derivatives). A master clock is derived from

the frame pulse. The video clock and master clock domain

are de-coupled by a FIFO. The audio clock can be derived

from the master clock. The video Packetized Elementary

Stream (PES) packetizer has to take care of the fullness of

the output buffer of the SAA6750H.

2000 May 03

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