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UPD72870

IEEE1394 1-CHIP OHCI HOST CONTROLLER

NEC => Renesas Technology 

µPD72870,72871

1. PIN FUNCTIONS

1.1 PCI/Cardbus Interface Signals: (52 pins)

(1/2)

Name

I/O

Pin No.

IOL

Volts(V)

Function

LQFP FPBGA

PAR

I/O 45

R4

PCI/Cardbus 5/3.3 Parity is even parity across AD0-AD31 and CBE0-CBE3. It is

an input when AD0-AD31 is an input; it is an output when AD0-

AD31 is an output.

AD0-AD31

I/O 11-14,

16-19,

24-27,

E1,E2,

F1,F2,

G1,G2,

PCI/Cardbus 5/3.3 PCI Multiplexed Address and Data

29,30,32, H1,H2,

33,49,50, K1,K2,

52,53, L1,L2,

55-58, M1,M2,

61-64,

66-69

N1,N2,

R5-R12,

T5-T12

CBE0-CBE3 I 22,35,47, J2,P2,P9,

-

60

T4

5/3.3 Command/Byte Enables are multiplexed Bus Commands &

Byte enables.

FRAME

I/O 36

P1

PCI/Cardbus 5/3.3 Cycle Frame is asserted by the initiator to indicate the cycle

beginning and is kept asserted during the burst cycle.

5

If Cardbus mode (CARD_ON = 1), this pin is should be pulled

up to VDD.

TRDY

I/O 38

R1

PCI/Cardbus 5/3.3 Target Ready indicates that the current data phase of the

transaction is ready to be completed.

IRDY

I/O 37

R2

PCI/Cardbus 5/3.3 Initiator Ready indicates that the current bus master is ready

to complete the current data phase. During a write, its assertion

indicates that the initiator is driving valid data onto the data bus.

During a read, its assertion indicates that the initiator is ready

to accept data from the currently-addressed target.

REQ

O8

D1

PCI/Cardbus 5/3.3 Bus_master Request indicates to the bus arbiter that this

device wants to become a bus master.

GNT

I7

D2

-

5/3.3 Bus_master Grant indicates to this device that access to the

bus has been granted.

IDSEL

I 23

J1

-

5/3.3 ID Select when actively driven, indicates that the IUHC is chip-

selected for configuration read/write transaction during the

phase of device initialization.

5

If Cardbus mode (CARD_ON = 1), this pin is should be pulled

up to VDD.

DEVSEL

I/O 39

T1

PCI/Cardbus 5/3.3 Device Select when actively driven, indicates that the driving

device has decoded its address as the target of the current

access.

STOP

I/O 42

T2

PCI/Cardbus 5/3.3 PCI Stop when actively driven, indicates that the target is

requesting the current bus master to stop the transaction.

Preliminary Data Sheet S13925EJ2V0DS00

13

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