UPD72870 Ver la hoja de datos (PDF) - NEC => Renesas Technology

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componentes Descripción

Lista de partido

UPD72870

IEEE1394 1-CHIP OHCI HOST CONTROLLER

NEC => Renesas Technology 

µPD72870,72871

Name

PORTDIS

I/O

Pin No.

LQFP FPBGA

I 105

H16

SUS_RESM I 106

G15

CPS

I 123

A15

Note Please refer to 4.1.3 CPS.

1.3 PHY Signals: (9 pins)

IOL

Volts(V)

Function

(2/2)

Port Disable

SUS_RESM = “1”

This selected state will be loaded to Disabled bit which

allocated PHY register Port Status Page.

1:Disable

At this time, all ports will be disabled (µPD72870: 3ports,

µPD72871: 1port).

SUS_RESM=“0”

PORTDIS has no effect.

Suspend/Resume Function Select

1 : Suspend/Resume On (P1394a draft 2.0 compliant)

0 : Suspend/Resume Off (P1394a draft 1.3 compliant)

-

- Cable Power Status Input Note

Name

I/O

Pin No.

IOL

Volts(V)

Function

LQFP FPBGA

TpBias0

O 128

C14

-

- Port-1 Twisted Pair Bias Voltage Output Note 2

TpBias1 Note1 O 127

B14

-

- Port-2 Twisted Pair Bias Voltage Output Note 2

TpBias2 Note1 O 126

A14

-

- Port-3 Twisted Pair Bias Voltage Output Note 2

RI0

- 121

A16

-

- Resistor0 for Reference Current Setting Note 3

RI1

5 FIL1

5 FIL0

- 122

B16

- 114

E15

- 115

E16

-

- Resistor1 for Reference Current Setting Note 3

-

- APLL Filter Terminal (No need to assemble)

-

- APLL Filter GND (No need to assemble)

XI

I 117

D15

-

- X’tal XI

XO

O 118

D16

-

- X’tal XO

Note 1. µPD72870 only. In µPD72871, it is open.

2. If unused port, please refer to 4.1.4 Unused Port.

3. Please refer to 4.5 RI0, RI1.

1.4 PHY Control Signals: (5 pins)

Name

I/O

Pin No.

IOL

LQFP FPBGA

PC0-PC2

I 93-95

K15,L15,

-

L16

CMC

I 96

K16

-

P_RESETB I 110

F16

Note 1. Please refer to 4.3 PC0-PC2, CMC.

2. Please refer to 4.4 P_RESETB.

Volts(V)

Function

3.3 Power Class Input Note 1

3.3 Configuration Manager Capable Note 1

PHY Power on Reset Input Note 2

Preliminary Data Sheet S13925EJ2V0DS00

15

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