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XR16C872

Dual UART with 1284 Parallel Port and Plug-and-Play Controller

Exar Corporation 

XR16C872

Preliminary

UART

The 872 UARTs are software compatible with the

industry standard 16C550 on power up or reset. Each

UART offers enhancements that are enabled through

its Enhanced Features Registers. These features in-

clude transmit and receive FIFOs of 128 bytes, pro-

grammable transmit and receive FIFO trigger level

from 0 to 128, baud rates with 1x or 4x clock pre-scaler,

automatic RTS flow control level with trigger hyster-

esis, automatic CTS flow control, automatic software

flow control, modem or general I/O interface control,

infrared IrDA encoder/decoder select with a software

option of inverting the decoder input logic level, sleep

mode, device ID and revision. The baud rate generator

input clock on both UARTs is supplied by a 7.3728 MHz

clock. This clock comes from an internal divided by 3

circuit that is fed by the crystal oscillator or external

clock input of 22.1184 MHz. Hence, the maximum

operating data rate is 460.8 Kbps.

Each UART provides 128 bytes of transmit and receive

FIFO memory instead of 16 in the 16C550. The larger

FIFO greatly reduces the bandwidth requirement of the

controlling CPU, increases system performance with-

out increasing the speed of the CPU, and reduces

overall power consumption. The 128 byte FIFOs also

simplify software manipulation of flash memory data

transfer where data page size is 128 bytes. Increased

performance is realized by the larger transmit and

receive FIFOs, FIFO counters, and programmable

FIFO trigger level. This allows the processor to handle

more networking tasks within a given time. For ex-

ample, the 16C550 with 16 byte receive FIFO, will

require 1.39 milliseconds to unload the FIFO (This

example uses a character length of 10 bits, including

start/stop bits at 115.2Kbps, [1/115200]x10x16). This

means the external CPU will have to service the

receive FIFO every 1.39 milliseconds. However with

the 128 byte FIFO in the 872 UART, the data buffer will

not require unloading/loading for 11.12 milliseconds.

This increases the service interval giving the CPU

additional time for other applications and reducing the

overall UART interrupt servicing time. In addition, the

FIFO counters and programmable FIFO trigger level

interrupt is uniquely provided for maximum data

throughput performance especially when operating in a

multi-channel environment.

UART Internal Registers

Each 872 UART has 24 internal registers for monitoring

and control. These resisters are summarized in Table

2 below. Twelve registers are compatible to those

already in the standard 16C550. These registers func-

tion as data holding registers (THR/RHR), interrupt

status and control registers (IER/ISR), a FIFO control

register (FCR), line control register and line status

register, (LCR/LSR), modem control and status regis-

ters (MCR/MSR), programmable baud rate control

registers (DLL/DLM), and an user defined scratch pad

register (SPR). Beyond the basic 16C550 features and

capabilities, the 872 UART offers enhanced feature

register set called TRG, FCTR, EFR, Xon1/2, Xoff1/2,

EMSR, TXCNT,RXCNT, REV and DID, Register

functions are fully described in the following para-

graphs.

Rev. P1.00

16

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