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XR16C872

Dual UART with 1284 Parallel Port and Plug-and-Play Controller

Exar Corporation 

Preliminary

XR16C872

Referring to Figure 4, the local UART (UARTA) starts

data transfer by asserting RTSA# (1). RTSA# is nor-

mally connected to CTSB# (2) of remote UART

(UARTB). CTSB# allows its transmitter to send data

(3). TXB data arrives and fills UART-A receive FIFO

(4). When RXA data fills up to its receive FIFO trigger

level, UARTA activates its RXA data ready interrupt (5)

and continues to receive and put data into its FIFO. If

interrupt service latency is long and data is not being

unloaded, UARTA monitors its receive data fill level to

match the upper threshold of RTS delay and de-assert

RTSA# (6). CTSB# follows (7) and request UARTB

transmitter to suspend data transfer. UART-B stops or

finishes sending the data bits in its transmit shift

register (8). When receive FIFO data in UARTA is

unloaded to match the lower threshold of RTS delay

(9), UARTA re-assert RTSA# (10) CTSB# recognizes

the change (11) and restarts its transmitter and data

flow again until next RX trigger (12). This same event

applies to the reverse direction when UARTA sends

data to UARTB with RTSB# and CTSA# controlling the

data flow.

Two interrupts associated with RTS and CTS flow

control have been added to give indication when RTS#

pin or CTS# pin is de-asserted during operation. The

RTS and CTS interrupts must be first enabled by EFR

bit-4, and then enabled individually by IER bit-6 and 7.

Automatic hardware flow control is selected by setting

bits 6 (RTS) and 7 (CTS) of the EFR register to logic 1.

If CTS# pin transitions from logic 0 to logic 1 indicating

a flow control request, ISR bit-5 will be set to logic 1 (if

enabled via IER bit 6-7), and the 872 UART will

suspend TX transmissions as soon as the stop bit of

the character in process is shifted out. Transmission is

resumed after the CTS# input returns to logic 0,

indicating more data may be sent.

The 872 UART offers a programmable flow control

trigger hysteresis while maintains compatibility to

16C650A. With the Auto RTS function enabled, an

interrupt is generated when receive FIFO reaches the

programmed RX trigger level. The RTS# pin will not be

forced to logic 1 (RTS Off) until it has reached the upper

limit of the hysteresis level. This delay action of

suspending remote transmitter increases data

throughput. The RTS# pin will return to a logic 0 (RTS

on) after RX data buffer (FIFO) is unloaded to the lower

limit of the hysteresis level. Under these described

conditions the UART will continue to accept data until

receive FIFO gets full. The Auto RTS function must be

started by asserting RTS# pin to logic 0 (RTS On). For

a full description of the hysteresis selection, see

EMSR bit 4 and 5 descriptions.

Software Flow Control

When software flow control is enabled, the 872 UART

compares one or two sequential receive data charac-

ters with the programmed Xon or Xoff-1,2 character

value(s). If receive character(s) match the pro-

grammed values, the transmitter will halt transmission

as soon as the current character has completed sent

out. When a match occurs, the Xoff-det interrupt (if

enabled via IER bit-5) flag will be set and the interrupt

output pin will be activated. Following a suspension

due to a match of the Xoff characters values, the UART

will monitor the receive data stream for a match to the

Xon-1,2 character value(s). If a match is found, the

UART will resume operation and clear the Xoff-det flag

(ISR bit-4).

Reset initially sets the contents of the Xon/Xoff 8-bit

flow control registers to logic 0. Following reset the

user can writes any Xon/Xoff value desired for soft-

ware flow control. Different conditions can be set to

detect Xon/Xoff characters and suspend/resume

transmissions. When double 8-bit Xon/Xoff characters

are selected, the 872 UART compares two consecu-

tive receive characters with two software flow control

8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls

TX transmissions accordingly. Under the above de-

scribed flow control mechanisms, flow control charac-

ters are not placed (stacked) in the user accessible RX

data FIFO.

If the receive FIFO is overfilling and flow control needs

to be executed, the 872 UART automatically sends a

Xoff message via the serial TX output to the remote

modem. The 872 UART sends the Xoff-1,2 characters

as soon as received data passes the programmed RX

FIFO trigger level. To clear this condition, the 872

UART will transmit the programmed Xon-1,2 charac-

ters as soon as receive data in the FIFO drops below

the programmed RX FIFO trigger level.

Rev. P1.00

19

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