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XR16C872

Dual UART with 1284 Parallel Port and Plug-and-Play Controller

Exar Corporation 

XR16C872

Preliminary

Special Feature Software Flow Control

A special feature is provided to detect a 8-bit character

when bit-5 is set in the Enhanced Feature Register

(EFR). When this character is detected, it will be

placed on the user accessible data stack along with

normal incoming RX data. This condition is selected in

conjunction with EFR bits 0-3. Note that the regular

software flow control should be turned off when using

this special mode by setting EFR bit 0-3 to logic 0.

The UART compares each incoming receive character

with Xoff-2 data. If a match exists, the received data

will be transferred to FIFO and ISR bit-4 will be set to

indicate detection of special character. Although the

Internal Register Table shows each register with eight

bits of character information, the actual number of bits

is dependent on the programmed word length. Line

Control Register (LCR) bits 0-1 defines the number of

character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits.

The word length selected by LCR bits 0-1 also deter-

mines the number of bits that will be used for the

special character comparison. Bit-0 in the X-registers

corresponds to the LSB bit for the receive character.

Interrupts

Interrupt conditions and priorities are indicated in the

interrupt status register (ISR), see Table 4. When the

transmitter interrupt is enabled the UART will issue an

interrupt to indicate that transmit holding register (THR)

is empty. This interrupt must be serviced before

continuing operations. The LSR register provides the

current singular highest priority interrupt only. It could

be noted that CTS and RTS interrupts have lowest

interrupt priority. A condition can exist where a higher

priority interrupt may mask the lower priority CTS/RTS

interrupt(s). Only after servicing the higher pending

interrupt will the lower priority CTS/ RTS interrupt(s) be

reflected in the status register. Servicing the interrupt

without investigating further interrupt conditions can

result in data errors.

When two interrupt conditions have the same priority,

it is important to service these interrupts correctly.

Receive Data Ready and Receive Time Out have the

same interrupt priority (when enabled by IER bit-0). The

receiver issues an interrupt after the number of charac-

ters have reached the programmed trigger level. In this

case the receive FIFO may hold more characters than

the programmed trigger level. Following the removal of

a data byte, the user should recheck LSR bit-0 for

additional characters. A Receive Time Out will not

occur if the receive FIFO is empty. The time out

counter is reset at the center of each stop bit received

or each time the receive holding register (RHR) is read.

The actual time out value is T (Time out length in bits)

= 4 X P (Programmed word length) + 12. To convert the

time out value to a character value, the user has to

consider the complete word length, including data

information length, start bit, parity bit, and the size of

stop bit, i.e., 1X, 1.5X, or 2X bit times.

Example -B: If the user programs the word length = 7,

with parity and one stop bit, the time out will be:

T = 4 X 7(programmed word length) + 12 = 40 bit times.

Character time = 40 / 10 [ (programmed word length =

7) + (parity = 1) + (stop bit = 1) + (start bit = 1) = 4

characters.

Programmable Baud Rate Generator

The 872 UART supports high speed modem technolo-

gies that have increased input data rate by employing

data compression schemes. For example a 33.6 Kbps

modem that employs data compression may require a

115.2 Kbps input data rate. A 128.0 Kbps ISDN modem

that supports data compression may need an input

data rate of 460.8 Kbps. The 872 UART supports

standard data rate from 50 to 460.8 Kbps with a main

clock of 7.3728 MHz which is internally derived from

the external crystal or clock of 22.1184 MHz. A single

baud rate generator provides for each UART transmit-

ter and receiver.

The 872 UART can be configured for internal or

external clock operation. For internal clock oscillator

operation, an industry standard microprocessor crystal

(parallel resonant, 20-33pF loading capacitance) is

connected externally between the XTAL1 and XTAL2

pin, see Figure 5. Alternatively, an external clock can

be connected to the XTAL1 pin to clock the internal

baud rate generator for standard or custom rates.

Rev. P1.00

20

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