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BT869KRF

Flicker-Free Video Encoder with Ultrascale™ Technology

Conexant Systems 

Bt868/Bt869

Flicker-Free Video Encoder with UltrascaleTM Technology

1.0 Functional Description

1.3 Circuit Description

1.3 Circuit Description

1.3.1 Overview

The Bt868/869 is a video encoder designed for TV output of non-interlaced

graphics data, such as that found in a PC or some set-top boxes. It incorporates

advanced filtering technology for flicker removal and overscan compensation

which allows high-quality display of non-interlaced images on an interlaced TV

display. The Bt868/869 accomplishes this by minimizing the flicker and providing

control of the amount of overscan so that the entire image is viewable.

The Bt868/869 consists of a Color Space Converter/Flicker Filter engine

followed by a digital video encoder. The Color Space Converter/Flicker Filter

contains the following:

• A timing converter

• Various horizontal video processing functions

• Flicker filter and vertical scaler for overscan compensation

The output of this engine is fed into a FIFO for synchronization with the

digital video encoder.

1.3.2 Reset

If the RESET* pin is held low for a minimum of two clock cycles, a timing reset

and a software reset is performed. During a timing reset, the serial interface is

held in the reset condition, the subcarrier phase is set to zero, and the horizontal

and vertical counters are held to the beginning of VSYNC of Field 1 (both

counters equal to zero). Counting resumes the next clock after rising RESET*.

The serial interface registers are reset to zero.

A software reset, which can be generated by setting the SRESET register bit,

initializes all the serial interface registers to zero (except for PLL_INT, which is

initialized to 0x0C). As a result, all output pins are three-state. The first 32

registers are then initialized to auto-configuration mode 0 (see the Auto

Configuration section). The EN_OUT bit must be set to enable the outputs. The

software reset can also be generated by setting the SRESET register bit.

A power-on reset is generated on power-up. The power-on reset generates both

a timing and a software reset. The power-on reset is generated by a time delay

circuit triggered after the supply voltage reaches a value sufficiently high enough

for the circuit to operate. As such, the device may not initialize to the default state

unless the power supply ramp rate is sufficiently fast enough. Therefore, a

hardware reset is recommended if the default state is required.

1.3.3 Timing Registers

After writing any registers, a timing reset is recommended by setting the T-bit.

100123B

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