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SMS24

Highly Programmble Voltage Supervisory Circuit

Summit Microelectronics 

SMS24

PIN DESCRIPTIONS

RESET#

MR#

This signal is an active-low open drain I/O. Whenever the

voltage on VCC is below the programmed threshold volt-

age the RESET# pin will be driven low. After VCC passes

through the threshold (in a positive direction) the RESET#

output will continue to be driven for the programmed time-

out period (tPTO). In most configurations RESET# is also

an input. Whenever it is driven low it will activate the reset

timer. The RESET# output will then be driven low by the

device for the programmed period. If the input pulse is of

shorter duration than tPTO, RESET# will continue to be

driven. If it is longer than tPTO, RESET# will be released

and follow the input back high.

RESET

This signal is an active-high open drain I/O. Whenever the

voltage on VCC is below the programmed threshold volt-

age the RESET pin will be driven high. After VCC passes

through the threshold (in a positive direction) the RESET

output will continue to be driven for the programmed time-

out period. In all configurations using RESET it is also an

input. Whenever it is driven high it will activate the reset

timer. The RESET output will then be driven high by the

device for the programmed period. If the input pulse is of

shorter duration than tPTO, RESET will continue to be

driven. If it is longer than tPTO, RESET will be released and

follow the input back low.

Manual Reset input is an active low input. Whenever it is

taken low it will generate a reset time-out.

VSENSE

This is a second voltage sense input connected to its own

comparator that has reference of 1.25V. The comparator

can be programmed to activate the VLOW# output either for

an over-voltage or under-voltage condition.

VLOW#

This is an active-low open-drain output that can be wire-

ORed with the RESET# output or tied directly to an

interrupt input.

WDI

This is the Watchdog Interrupt input. Whenever a transi-

tion occurs on WDI the watchdog timer will be cleared. If

the device does not receive an interrupt before tWDTO the

device will drive the reset output(s). The period tWDTO is

programmable for four basic values. It can also be placed

into an idle mode, facilitating system debug, and allowing

a system time to configure itself after a power-on.

WP

This is an auxilliary Write lockout input pin. When held high

no writes will occur.

RESET#1 & RESET#2

SCL

These signals are active-low open drain outputs (not I/Os).

These outputs are only available to Device Code 100, and

are both set to a low state by any one of three events: VCC

below trip level, VSENSE < 1.25V, or MR# strobed low.

The serial interface clock input.

SDA

The serial interface data I/O.

6

2048 2.4. 3/1/01

SUMMIT MICROELECTRONICS, Inc.

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