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SMS24

Highly Programmble Voltage Supervisory Circuit

Summit Microelectronics 

SMS24

Table 3. Programming Register 1

MSB

7

6

5

4

3

2

1

LSB

0

LOCK

OV

Add

DT

WD2

WD1

WD0

Watchdog Timeout Seconds

Watchdog Timeout Bits

OFF or Idle Mode à

0

0

x

0.4s à

0

1

1

0.8s à

1

0

0

1.6s à

1

0

1

3.2s à

1

1

0

6.4s à

1

1

1

x

0

Device Type Address 1010

x

1

Device Type Address 1011

x

0

Responds to Address Pin Bias

x

1

Ignores Address Pin Bias

0

VSENSE Triggers > Threshold (1.25V)

1

VSENSE Triggers < Threshold (1.25V)

0

PR Registers Open for Writing

x

1

PR Registers Writing Lockout

x

x

2048 Table03 2.0

MEMORY OPERATION

START and STOP Conditions

The SMS24 memory is configured as a 2K x 8 array. Data

is received and transmitted via an industry standard two-

wire interface. The bus was designed for two-way, two-

line serial communication between different integrated

circuits. The two lines are a serial data line (SDA), and a

serial clock line (SCL). The SDA line must be connected

to a positive supply by a pull-up resistor, located some-

where on the bus

Input Data Protocol

When both the data and clock lines are high, the bus is said

to be not busy. A high-to-low transition on the data line,

while the clock is high is defined as the “START” condition.

A low-to-high transition on the data line while the clock is

high is defined as the “STOP” condition.

SCL

START

Condition

STOP

Condition

Configuring and programming the SMS24 is done using

the 2-wire serial interface. The device type address for this

operation is 1001BIN.

The protocol defines any device that sends data onto the

bus as a “transmitter” and any device that receives data as

a “re ceiver.” The device controlling data transmission is

called the “master” and the controlled device is called the

“slave.” In all cases the SMS24 will be a “slave” device,

since it never initiates any data transfers.

One data bit is transferred during each clock pulse. The

data on the SDA line must remain stable during clock high

time because changes on the data line while SCL is high

will be interpreted as a start or a stop condition.

SDA In

2046 Fig01 2.0

Figure 1. START and STOP Conditions

Acknowledge (ACK)

Acknowledge is a software convention used to indicate

successful data transfers. The transmitting device, either

the master or the slave, will release the bus after transmit-

ting eight bits. During the ninth clock cycle the receiver will

pull the SDA line low to ACKnowledge that it received the

eight bits of data.

8

2048 2.4. 3/1/01

SUMMIT MICROELECTRONICS, Inc.

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